Nanoscale strain analysis by TEM for reduction of power consumption in 180nm CMOS low power embedded flash technology

• Unité de recherche: INNOSUISSE
• Numéro de projet: 13496.1;6 PFFLE-NM
• Titre du projet anglais: Nanoscale strain analysis by TEM for reduction of power consumption in 180nm CMOS low power embedded flash technology

Description succincte (Anglais)

Nanoscale strain analysis by TEM for reduction of power consumption in 180nm CMOS low power embedded flash technology

Description succincte (Français)

Nanoscale strain analysis by TEM for reduction of power consumption in 180nm CMOS low power embedded flash technology

Résumé des résultats (Abstract) (Anglais)

In order to further reduce consumption current in ICs fabricated with EM Microelectronic new 180nm Embedded Flash Technology, we want to: o Develop a local strain measurement method (microscopy by TEM) at CIME-EPFL o Fabricate and measure dedicated samples with EM 180nm Embedded Flash Technology, including deviation from standard flow and specific layout o Identify stressing operations, implement low-stress recipes in production line and adjust design rules for future circuits

Résumé des résultats (Abstract) (Français)

In order to further reduce consumption current in ICs fabricated with EM Microelectronic new 180nm Embedded Flash Technology, we want to: o Develop a local strain measurement method (microscopy by TEM) at CIME-EPFL o Fabricate and measure dedicated samples with EM 180nm Embedded Flash Technology, including deviation from standard flow and specific layout o Identify stressing operations, implement low-stress recipes in production line and adjust design rules for future circuits