Partenaires et organisations internationales
(Anglais)
|
Thomson-CSF Microelectronique (F), SIEMENS AG (D), IMC (S), Strand (S), NMRC (IE), R. Hirschmann GmbH & Co. KG (D), C.A.E.N. Microelectronica (I), ETH Zürich (CH)
|
Résumé des résultats (Abstract)
(Anglais)
|
The main LAP objective was the development and demonstration of a low cost high-density substrate manufacturing technology for 1st-level die assemblies. The cost target for the high-volume production of this high-density interconnect (HDI) substrates is as low as US$1/in². It was obtained by increasing the wafer-scale panel sizes of today to panel areas up to 24x24 in². While this largest thinkable panel size remained an object of studies and experiments, 16x16 in², 12x12 in², and 8in in diameter have been introduced to the HDI production in the year 2000. 50µm pitch and via/land dimensions were achieved by HDI processing on the panels. The substrate technologies developed allows for a wide range of packaging options from inserted substrates into transfer-molded packages to integrated area array packages using metal or laminate cores. The suitability of the LAP technology was demonstrated with three products from the sectors communications, instrumentation, and telecommunication.
The Swiss contribution was the electrical (work package 3) and economical (work package 1) evalua-tion of the LAP technology. Due to ETH's cost modelling experience and its neutral position to the manufacturers, ETH did the cost benchmarking for the LAP technology in WP1, comparing the cost against existing lines and competitors. In WP3, ETH assessed the electrical (especially RF perform-ance) of the LAP technology. To do so, special test vehicles have been designed and measured ad-dressing the specific problems anticipated for LAP processing (handling problems, misalignment, stress induction, to name just a few).
During its third year, the project has achieved the following milestones:
- final cost benchmarking of the manufacturers' new LAP lines,
- test vehicle and demonstrator production on 16x16 in² and 12x12 in² panels and on 8in wafers,
- test vehicle production on 24x24 in² panels for optimisation of equipment and materials,
- final RF characterization of test vehicles, including integrated passives, up to 110GHz,
- compilation of design rules and RF design guidelines for the LAP technologies,
- reliability qualification according to the demonstrator application requirements,
- production of communication, instrumentation, and telecommunication demonstrator
|
