Metrology for manufacturing 3D stacked integrated circuits

• Unité de recherche: SEFRI
• Numéro de projet: 15.0208

Résumé des résultats (Abstract) (Anglais)

Performance requirements in the electronics industry can no longer be met by downsizing conventional semiconductor devices. More compact 3D microchips (also known as 3D integrated circuits) are being developed to meet requirements, offering reduced power consumption and increased speed over their 2D counterparts. 3D integration technology uses a type of electrical connection, known as a through-silicon vias (TSVs), to vertically stack chips and produce 3D integrated circuits with an optimum balance between cost, functionality, performance and power consumption. While this technology is already used in applications such as imager sensors and memory, its extension into new areas will require a greater density of smaller TSVs with higher aspect ratios. This project aimed to develop traceable measurement capabilities for detecting structural and chemical defects in high aspect ratio TSVs, and new methods to accurately characterise thermal and electrical properties at the nanoscale. This metrological infrastructure will allow Europe to play a more important role in the supply chain for future information systems built using highly dense electronics, and will create an enduring competitive advantage for Europe.