EMPIR-14IND07: Metrology for manufacturing 3D stacked integrated circuits (3D Stack)

• Forschungsstelle: METAS
• Projektnummer: F-5217.30062
• Projekttitel Englisch: EMPIR-14IND07: Metrology for manufacturing 3D stacked integrated circuits (3D Stack)

Schlüsselwörter (Englisch)

3D technology; 3D heterogeneous integration; TSVs; wafer stacking; metrology; nanoelectronics; nanoscale characterization

Kurzbeschreibung (Englisch)

In February 2014, the European Electronic Leaders Group, representing the main companies in the sector, identified 3D integration of heterogeneous semiconductor technologies as the key opportunity for growth in Europe. 3D integration technology uses copper Through Silicon Vias (TSV) to electrically connect a stack of chips-bonded semiconductor wafers and dies to produce 3D stacked integrated circuits (3D-SICs) with an optimum combination of cost, functionality, performance and power consumption.

While this technology is already used in imagers, memories and MEMS, its extension into new areas will require a much larger density of higher aspect-ratio, smaller TSVs. This creates new metrological issues related to the dimensional and electrical characterisation of these TSVs and to the characterisation of heat caused by the higher current density in those structures.
Another aspect of this technological vision is that each function of the 3D stack samples (i.e. memory, sensor, biochip) can be manufactured independently at the right node (the node is the number representing the lowest size of the chip features) and in an optimised production line. 3D integration will allow them to be combined into a single compact system, with logic devices, memories, imagers and MEMS structures from different wafers (from various foundries) using different manufacturing processes. However, this introduces new traceability requirements in the metrology (e.g. dimensional measurement) for 3D integration.

This is a joint research project carried out in the framework of the European Metrology Programme for Innovation and Research (EMPIR) (see:http://www.euramet.org/research-innovation/empir/). The EMPIR initiative is co-funded by the European Unions's Horizon 2020 research and innovation programme and the participating states. METAS is one of the project partners in the project.

Projektziele (Englisch)

his project addresses these needs by developing the traceable measurement capabilities for structural and chemical defects inspection in high aspect ratio through silicon vias (HAR TSV) and wafer/chip bonding and thinning. The project will also develop new accurate measurement techniques for thermal and electrical materials characterisation at the nanoscale of the TSVs with the following objectives;

1. To develop reliable 3D characterisation techniques, protocols and standards to accurately measure (at micron and submicron resolution) dimensional and structural properties of high aspect ratio (HAR>10) TSV interconnects before and after Cu filling: sidewall roughness, via shape, seed- and barrier-layer thickness, sidewall layer conformity, void detection and characterisation, grain size and grain boundary character distribution of the copper grains, crystalline structure, dislocations, stress around the TSV. In addition, for 3D-SICs with high density TSV interconnects, it is important to consider non-destructive wafer measurements as well as statistical data collection to enable the implementation of the measurement techniques in a production environment.
2. To develop methods to accurately measure the electrical and thermal transport properties of nanostructured copper TSV interconnects in order to establish traceable measurements of electrical conductivity and temperature change in copper as a function of the current density. Modelling of thermal transport in those structures will help to identify the various thermal scattering mechanisms in nanostructured copper grains.
3. To develop metrology tools, protocols and standards for high lateral and z resolution (sub microns for x-y, nm for z) non-destructive wafer to wafer alignment control before and after bonding as well as the characterisation of the bonding quality of wafers and dies: parameters at die level such as curvature, surface roughness and flatness which might need to be coupled with wafer level information; wafer/die contamination before bonding; wafer/die interface defectivity and adhesion after bonding; local stress and thermal dissipation at the interface of bonding wafers and dies will also be considered.
4. To provide traceable metrology for thickness uniformity control and for the surface quality of wafers/dies thinning (in the presence of circuits) and measurement techniques related to stress relaxation, crystalline defects and surface contamination.
5. To engage with the semiconductor industry and others to facilitate the take up of the technology and measurement infrastructure developed by the project, to support the development of new, innovative products utilising 3D-stacked ICs, thereby enhancing the competitiveness of EU industry.

Abstract (Englisch)

Technical deliverables focused on thorough investigation of Through Silicon Vias (TSVs) including their dimensions, electrical properties, interconnects and general integrity. In order to contribute to this general characterization METAS performed the following activities:

• METAS has developed sample definitions and design specifications. According to those, project partners fabricated samples for the different tasks.
• A wide range of different TSV samples has been measured within the project.
• In the course of the project, the SMM was upgraded with a vibration isolation platform and an acoustic enclosure. The resulting improvements in resolution were demonstrated with calibration sample provided by METAS’ AFM group.
• Out of schedule a new additional x-y positioner system with travel ranges up to 25 mm has been installed in the SMM. This allows performing measurement series on multiple features distributed on the wafer scale. It is also possible to perform large area, low resolution scans with these positioners.
• Strong evidence of grains and their boundaries in bumps was found with the SMM.
• By analyzing an individual TSV it was found that the type (length, quality) of its interconnect to the neighboring TSV could be identified relative to the different available interconnect types.
•       Dimensional measurements on bump samples have been performed with the White Light Interferometer (WLI). To properly analyze the data and extract a maximum of information an elaborate analysis routine using FFT and Gaussian filtering was programmed. Good results on the flatness of the substrate wafer and the height of the bumps were achieved. This is especially remarkable, because the bumps are dome-shaped and the WLI works best on flat surfaces but this restriction could be mitigated by the self-programmed analysis routine.

Umsetzung und Anwendungen (Englisch)

Project partner CEA showed interest in the WLI analysis routine developed at METAS. This may lead to future collaboration.

In the field of failure analysis for TSVs and their networks, project partners Fraunhofer and imec showed strong interest in the METAS work identifying grains and interconnect quality. Based on this some follow-up work is possible.

Publikationen / Ergebnisse (Englisch)

none at project end.