Partner und Internationale Organisationen
(Englisch)
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Universita degli studi di Pisa (I), National Microelectronics Research Centre, Cork (IRL),
Max-Planck-Institut für Festkörperforschung, München (D), Bayerische Julius-Maximilians Universität Würzburg (D),
TU Wien IME (A)
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Abstract
(Englisch)
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As miniaturization of electronics devices progresses from the sub-micron to the few nanometre scale, the influence of quantum mechanical effects on device operation becomes so dominating that 'traditional' semiconductor devices suffer severe performance degradation or cease to function at all. Thus it is essential that devices be developed which operate because of quantum mechanical effects rather than in spite of them. Various candidate structures for such devices have been proposed; but often they cannot be manufactured in a reproducible way. It is the aim of the simulation work package of NANOTCAD to develop a simulation framework that can be used to study candidate structures for semiconductor based nanoelectronics devices in order to find out whether or not they might be suitable for ultra large scale integration.
In the second year of the project a single electron structure on an AIGaAs/GaAs heterostructure fabricated and characterized by the group in WGrzburg was simulated with the SET simulation package SIMNAD of ETHZ and compared with simulation results obtained by the group in Pisa. Because of the possibly large numbers of electrons and single particle orbitals involved in GaAs devices, a Monte Carlo integration scheme for the free energies and Gibbs probabilities was developed and implemented in order to handle the computational expense for the explicit evaluation of the phase space average. The calibration of the surface pinning energy to a value, that yields the experimental conductance through the source/drain Quantum Point Contacts (QPCs) turned out to be crucial for a good simulation of the SET structure. The QPC was treated with a 2DEG-1DEG-2DEG quantization model, the floating gates being eliminated from the grid. The pinning energy was fixed in such a way that only one transverse mode remained in transmission. This value then was used for the SET simulation, where the full 2DEG-1 DEG-ODEG-1 DEG-2DEG domain decomposition was applied for the computation of charge densities, charging curves, and gate-to-dot capacities. It was found that the threshold voltage is very sensitive to the value of the surface pinning energy: 2 mV will change the electron number by 1 and, correspondingly, the threshold voltage by about 10 mV. Convergence at 300 mK turned out to be extremely poor, but rapidly improves with increasing temperature.
An SOl single electron transistor fabricated in TGbingen within the MEL-ARI FASEM project (APL 76, 2065 (2000)) was simulated with the SET simulation package SIMNAD of ETHZ and compared with simulation results obtained by the group in Pisa. Different geometries were built and their impact on the device characteristics was studied. An automatic construction scheme for 3D transfer Hamiltonians was developed and implemented to overcome spurious states localized in the artificial potential well between the tunneling barrier delimiting the active quantum dot volume and the hard-wall potential used for Dirichlet boundary conditions. An improved connection condition in the overlap region between wire and quantum dot region was also implemented. The linear response conductance of the SOl SET was simulated with constant tunneling rates assuming complete ionization of dopants. Extracted gate-to-dot capacities were in good agreement both with the measured values and the simulation results by the Pisa group. Both simulators also yield the same position of the first conductance peak, if the same ionization model is used.
As miniaturization of electronics devices progresses from the sub-micron to the few nanometre scale, the influence of quantum mechanical effects on device operation becomes so dominating that 'traditional' semiconductor devices suffer severe performance degradation or cease to function at all. Thus it is essential that devices be developed which operate because of quantum mechanical effects rather than in spite of them. Various candidate structures for such devices have been proposed; but often they cannot be manufactured in a reproducible way. It is the aim of the simulation work package of NANOTCAD to develop a simulation framework that can be used to study candidate structures for semiconductor based nanoelectronics devices in order to find out whether or not they might be suitable for ultra large scale integration.
In the second year of the project a single electron structure on an AIGaAs/GaAs heterostructure fabricated and characterized by the group in WGrzburg was simulated with the SET simulation package SIMNAD of ETHZ and compared with simulation results obtained by the group in Pisa. Because of the possibly large numbers of electrons and single particle orbitals involved in GaAs devices, a Monte Carlo integration scheme for the free energies and Gibbs probabilities was developed and implemented in order to handle the computational expense for the explicit evaluation of the phase space average. The calibration of the surface pinning energy to a value, that yields the experimental conductance through the source/drain Quantum Point Contacts (QPCs) turned out to be crucial for a good simulation of the SET structure. The QPC was treated with a 2DEG-1DEG-2DEG quantization model, the floating gates being eliminated from the grid. The pinning energy was fixed in such a way that only one transverse mode remained in transmission. This value then was used for the SET simulation, where the full 2DEG-1 DEG-ODEG-1 DEG-2DEG domain decomposition was applied for the computation of charge densities, charging curves, and gate-to-dot capacities. It was found that the threshold voltage is very sensitive to the value of the surface pinning energy: 2 mV will change the electron number by 1 and, correspondingly, the threshold voltage by about 10 mV. Convergence at 300 mK turned out to be extremely poor, but rapidly improves with increasing temperature.
An SOl single electron transistor fabricated in TGbingen within the MEL-ARI FASEM project (APL 76, 2065 (2000)) was simulated with the SET simulation package SIMNAD of ETHZ and compared with simulation results obtained by the group in Pisa. Different geometries were built and their impact on the device characteristics was studied. An automatic construction scheme for 3D transfer Hamiltonians was developed and implemented to overcome spurious states localized in the artificial potential well between the tunneling barrier delimiting the active quantum dot volume and the hard-wall potential used for Dirichlet boundary conditions. An improved connection condition in the overlap region between wire and quantum dot region was also implemented. The linear response conductance of the SOl SET was simulated with constant tunneling rates assuming complete ionization of dopants. Extracted gate-to-dot capacities were in good agreement both with the measured values and the simulation results by the Pisa group. Both simulators also yield the same position of the first conductance peak, if the same ionization model is used.
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