Abstract
(English)
|
Objective:
The 3rd generation mobile communication standards to be introduced in 2002 combine advanced modulation methods (CDMA) with wide spectrum allocation to achieve high bit rate mobile data communication. Deep sub-micron CMOS technologies, on the other hand, promise to enable the reduction of the cost, weight and size of RF transceivers through improved level of integration. This project aims to develop the necessary know-how in both advanced RF transceiver architecture for wide-band CDMA mobile communication standard and its efficient implementation using deep sub-micron CMOS technologies.
In the fast growing and the high demanding world of mobile communications both vendors and customers push for smaller and cheaper mobile hand sets with longer standby and talk times. With the higher carrier frequency of 2GHz, wider signal bandwidth of 5MHz or more and dramatically increased requirement for digital signal processing, the pressure is even higher on the design of the RF and digital integrated circuits. User-friendliness, multiple-standard operation, co-integration of services will be the challenges in the coming 2-3 years. In order to fulfil such requirements, the highest level of integration together with a short design time is required. CMOS process has for a long time been the standard process for digital signal processing. Due to rapid technology improvement, CMOS is also becoming reality for the RF part of the mobile transceiver's chip set.
The objective of this project is threefold. Firstly the project aims to develop a transceiver architecture best optimised to both wideband CDMA standard and deep sub-micron CMOS implementation. Secondly the project will research and demonstrate the feasibility of deep sub-micron CMOS technology in the radio part of cellular mobile communication transceivers. Thirdly it aims to achieve the highest level of integration in the base band and IF parts of the radio transceiver in a highly demanding, mixed signal environment.
Approach:
To achieve this goal advanced methodology and innovative solutions, together with a top-down system engineering will be used, specially for reduction of a cross-talk between digital and analogue circuits.
The comparison between BiCMOS and CMOS performance in two Gigahertz frequency range will be done by designing RF building blocks both in BiCMOS and CMOS technologies. The following RF building blocks will be designed: low noise amplifier, integrated voltage control oscillator, frequency synthesiser, I/Q modulator, I/Q demodulator, power amplifier driver with a gain control and mixer.
On the base band side that will be developed only in CMOS, special care will be taken to solve problems in a mixed signal (digital and analogue) environment. The following building blocks will be developed for base band and IF parts: A/D and D/A converters, integrated base-band filters for transmitter and receiver paths and base-band and IF gain-controlled amplifiers.
All building blocks will be designed such that they can be easily reused in other similar projects in order to reduce design time by sharing know-how. Furthermore special attention will be paid to reducing power consumption and chip area in order to come up with a competitive design.
Work progress:
Project phase 1, containing the system modelling and simulation, has been successfully completed after 6 months. As results a zero IF receiver architecture has been chosen and the specification for the building blocks have been defined.
Project phase 2 with 9 months duration has been successfully completed mid 2001. It is divided into 4 working packages, WP2-WP5, for the following 4 areas of work: transmit base band (WP2), Transmit RF (WP3), Receive Base Band (WP4) and Receive RF (WP5). For all parts a circuit implementation in CMOS has been carried out. The ICs have been produced and tested. They all worked as planned with one minor exception. Designed circuits comprise two LNAs, Rx and Tx Mixer, base band Rx and Tx filter, VCO, pre-scaler and PLL.
For project phase 3 and 4 it was decided to migrate the circuits to a more advanced CMOS technology in order to further optimise the power consumption. Two integrations have been carried out as planned. Testing is delayed because of the extended fabrication times of the circuits.
Exploitation:
There are two different types of results expected, a front-end chip on one hand, but also experiences in RF CMOS design and in handling the design challenges of high level RF/analogue/digital integration as well.
It is the interest of Infineon to make the broadest use possible of the hardware as well as of he know-how gained within this project. The front-end chip will directly go into a product design and finally volume fabrication of a complete W-CDMA chipset based on advanced CMOS technologies. The building blocks will be re-used, maybe with some modifications, for other projects like home radio which is in the same carrier frequency range. The expertise in handling the complex problems of co-simulation and co-integration of RF, analogue and digital blocks on one chip will be of crucial importance for all similar projects and products.
The academic partners will broaden their expertise in the development of complex system chips in advanced technologies and will enhance their knowledge about industrial needs. This project will not only contribute to advanced research activities, but also help to keep the most qualified and motivated researchers and Ph.D. students in Europe for education and research a the university and following industrial work instead of migrating to the U.S. The gained know-how will also contribute to a higher level of teaching and education with emphasis to practical implementation in lectures and courses at university.
|
