Abstract
(Englisch)
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I) Substrate Modeling Techniques for RF integrated circuits: The relentless move to a single-chip integration of such heterogeneous designs as Digital, Analog, RF front-ends, etc. has opened the door to a host of challenging substrate noise coupling effects. In this abstract, we will point out the methodologies and the tools for substrate coupling analysis, that has been developed in SODERA. A new approach, which combines a detailed physical comprehension of the noise coupling effects and an improved of Boundary-Element-Method (BEM), to accelerate the substrate model extraction and to avoid the dense matrix storage, has been developed. Extraction times 100´ faster and with 10´ less memory usage than classical finite difference method, have been demonstrated on a test design. Moreover, the weak dependence of its efficiency with respect to the complexity of the handled chip, makes that it can be one of the most suitable method to verify Complex Mixed-Signal System-On-a-Chip. A first version of a substrate analysis package HspeedEx [1], which uses the algorithms of the method, was developed and tested. On the other hand, we have proposed a methodology that uses a suite of commercial tools with HspeedEx, in an efficient manner to deal with substrate noise problems. The first ultimate objective of the methodology was to verify, early in design flow, if the functions of the system will be corrupted by the noise coupling. This condition, enables us to make necessary design changes before physical implementation of the system, resulting in a significant reduction of the delay and the cost of the operation. However, the substrate coupling is also a global problem that depends on full-chip layout, technology used, and package parasitics. Therefore, a strategy considering all these aspects in an iterative noise-immunity optimization loop, at full-chip level, has been proposed. The methodology is integrated with a typical design flow: Cadence/SubstrateStorm of Simplex for layout, geometrical parameters, HspeedEx for a fast substrate modeling and Advanced Design System for system and electrical simulations. A successful test of the methodology to help a single-chip integration of a transceiver dedicated to ISM applications[2], was performed.II) Medium-Power Amplifier for WCDMA: As part of the work on the bias adaptation or envelope tracking, a new medium power amplifier, MPA, for 1.9GHz working in class A, AB has been designed and tested. The heart of the PA is a two-BJT current mirror with a transition frequency of 25GHz and a 1:15 ratio. The current mirror is required for the MPA to work properly in an envelope-tracking configuration. It provides thermal compensation for large power variations and also presents a low source impedance for the transistor input bias point improving its power output compression characteristic.The design of this MPA, free of thermal distortion, has been useful to figure out the load it presents for the DC-DC converter. The comprehension of the load is essential for the design of the DC-DC converter as it behaves in a non-linear fashion. The non-linearity comes from the intrinsic exponential law (BJT) and the conduction angle or the class in which the PA works. For a single tone, as the output power increases, the DC current drawn by the MPA increases in a non-linear way with respect to the DC-collector voltage, which is proportionally adapted to put back the output compression.The ratio between the applied DC-collector voltage and the current drawn by the MPA represents the load. A model for the non-linear load has been developed in order to perform system and circuit simulations. The model allows the changing of many parameters like the MPA's gain, quiescent current, coupler and DC-DC converter analog gain in order to see their influence on the DC-DC output response. With the experience of the previous discrete version of the DC-DC converter and the design of the new PA, a new DC-DC converter along with the envelope detector for 1.9GHz and analog processing has been simulated and integrated in a 0.35um CMOS process. With the help of the system simulation, the integrated DC-DC converter has been optimized to respond to fast envelope variations while driving a non-linear load. The typical output current ranges from 100mA (MPA quiescent current) to 150mA (peak MPA current) and the filtered output voltage from 1.25 to 3V. The envelope bandwidth, as well as the RF output power, results from tradeoffs. Typically, the envelope bandwidth is greater than 1MHz and the output power is 50mW.[1] A. Koukab, C. Dehollain, M. Declercq ' HspeedEx: A High-Speed Extractor for Substrate Noise Analysis in Complex Mixed-Signal SOC)' , IEEE/ACM 39th Design Automation Conference 2002, June 2002.[2] A. Koukab, M. Declercq, C. Dehollain 'Analysis and Improvement of the Noise Immunity in a Single-Chip Super-Regenerative Transceiver' IEE Proc.-Circuits Devices Syst., October 2001, Vol. 148, No. 5, pp. 250-254.
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