ASILUM: Advanced signal processing schemes for link capacity increase in UMTS

• Unité de recherche: PCRD EU
• Numéro de projet: 99.0097-1
• Titre du projet anglais: ASILUM: Advanced signal processing schemes for link capacity increase in UMTS

Mots-clé (Anglais)

UMTS/UTRA FDD - TDD; interference mitigation; wideband directional channel model

Autre Numéro de projet (Anglais)

EU project number: IST-1999-10741

Programme de recherche (Anglais)

EU-programme: 5. Frame Research Programme - 1.2.4 Essential technologies and infrastructures

Description succincte (Anglais)

See abstract

Partenaires et organisations internationales (Anglais)

Coordinator: CEA-LETI (F)

Résumé des résultats (Abstract) (Anglais)

The aim of this project is to validate new transceiver concepts, for both base stations and mobile terminals, which increase through efficient interference mitigation schemes the capacity of the future generation of the Universal Mobile Telecommunications System (UMTS). For this end, a software-based simulation platform running a number of competitive techniques has been designed in accordance with the UMTS physical layer specifications and is currently being implemented in COSSAP. In view of the implementation of the link level evaluation platform, some simplifying assumptions have been made concerning the reference scenarios to be investigated. Therefore, only a single cell is considered in which traffic is continuous and of constant rate, and intracell interference varies on a slot-by-slot basis, while intercell interference is modeled as additive white Gaussian noise. The proposed interference mitigation schemes for the frequency-division duplex mode to be validated may use one or several receiving antennas. In the latter case, either the resulting spatial diversity or the directional information is exploited to further improve the respective link quality. The performance of the interference mitigation algorithms will be assessed by means of different criteria, such as e.g. the bit-error rate, frame-error rate, and estimation errors. Finally, a figure of merit for a given scheme will be determined which expresses the obtained capacity gain with respect to implementation complexity quantified e.g. by the number of floating-point operations needed to detect one bit, the required memory, and the necessary silicon area for a hardware implementation of the algorithm.

Références bases de données (Anglais)

Swiss Database: Euro-DB of the
State Secretariat for Education and Research
Hallwylstrasse 4
CH-3003 Berne, Switzerland
Tel. [phone]
Swiss Project-Number: 99.0097-1