ITTI: Interactive terrestrial TV integration

• Unité de recherche: PCRD EU
• Numéro de projet: 99.0014
• Titre du projet anglais: ITTI: Interactive terrestrial TV integration

Mots-clé (Anglais)

Digital television return channel; DVB-T; SFDMA; VHDL; FPGA

Autre Numéro de projet (Anglais)

EU project number: AC321

Programme de recherche (Anglais)

EU-programme: 4. Frame Research Programme - 1.2 Communications technologies

Description succincte (Anglais)

See abstract

Autres indications (Anglais)

Full name of research-institution/enterprise:
Scuola universitaria professionale della Svizzera italiana SUPSI
Dipartimento Informatica ed Elettronica

Partenaires et organisations internationales (Anglais)

STMicroelectronics, Politecnico di Torino, CCETT, LEP CNET, COMATLAS, TDF-C2R, ERA Technology
Panasonic OWL, ITIS, UPM-DIT, TBS, RTE

Résumé des résultats (Abstract) (Anglais)

The european project iTTi (interactive Terrestrial Television integration) was started in 1998 as part of the ACTS (Advanced Communication Technologies and Services).
The project goal was the specification and practical demonstration of a wireless return channel for the terrestrial digital television. In the proposed technique, the direct (downstream) channel is the european standard DVB-T, while the return (upstream) channel is based on a new technique, namely the SFDMA (Synchronous Frequency Division Multiple Access). The core of the system is the SFDMA modulator, which is a unit composed of two well distincts sub-units. The base-band modulator, which takes input from a MAC (media access control) unit (usually a microcontroller), and elaborates these digital data through a cascaded serie of DSP blocks (convolvers, FFT and digital filters among others). Following the base-band modulator, the RF modulator translates the signal to the UHF band for the antenna emission.
The SUPSI contribution to the project was the architectural study for an efficient implementation of the base-band part of the SFDMA modulator. Even if the study was carried out for an FPGA implementation, a future ASIC realization was always kept in mind. This, because the digital television is strictly in the consumer electronics domain and calls for cheap high volume ASIC implementations.
The chosen realization architecture includes an hardwired convolver, a microprogrammed datapath unit for the FFT calculation, followed by another hardwired digital Nyquist filter. Memories required for intermediate results storage are implemented as external blocks (which will become compiled macrocells in a full-custom ASIC realization).
The available result is an RTL VHDL code for the logic part of the modulator. The obtained circuit requires about 80'000 gates for the logic part only (without counting the memories).

Références bases de données (Anglais)

Swiss Database: Euro-DB of the
State Secretariat for Education and Research
Hallwylstrasse 4
CH-3003 Berne, Switzerland
Tel. [phone]
Swiss Project-Number: 99.0014