MADBRIC: Mixed analog digital broadband integrated circuit

• Unité de recherche: PCRD EU
• Numéro de projet: 98.0225
• Titre du projet anglais: MADBRIC: Mixed analog digital broadband integrated circuit

Mots-clé (Anglais)

High-speed digital communication; analog-digital converter; digital-analog converter

Autre Numéro de projet (Anglais)

EU project number: 29649

Programme de recherche (Anglais)

EU-programme: 4. Frame Research Programme - 1.3 Telematic systems

Description succincte (Anglais)

See abstract

Partenaires et organisations internationales (Anglais)

Coordinator: DS2 (E)

Résumé des résultats (Abstract) (Anglais)

The demand for having access to internet services has been growing rapidly while no signs of any changes of this trend are visible. The most important bottleneck of a rapid growth, however, is the so-called last mile, which is the connection of the individual customers to high-speed backbone networks. The preferable solution to circumvent this bottleneck is the utilization of existing wire connections, such as TV cables, telephone lines or power lines. The MADBRIC project concentrates on the development of a silicon chipset for high-speed digital communication services over power lines.
The most important analog building blocks at both ends of the communication path, namely at the customer premises and at the utility substation, where the connection to the high-speed backbone takes place, are different types of analog-to-digital and digital-to analog converters. The development of these converters is the task of ETH Zürich.
At the utility substation, high-speed data converters are necessary due to the large bandwidth requirement. A four-stage, 13-bit pipelined A/D converter has been designed using an advanced digital 0.25 µm CMOS process with a single layer of polysilicon and six layers of metal. The maximum conversion rate is 5 Msample/s. The differential non-linearity is 0.5 LSB without calibration or trimming.
The transmit path is fed by a 14-bit 50 Msample/s current-scaling D/A converter that has been designed in the same technology. This D/A converter utilizes an architecture with floating current sources, making an on-chip calibration in the background (i.e. simultaneously with the normal operation) possible.
Compared to the utility substation, the bandwidth requirements are low in the customer premises equipment. Therefore, a S?-architecture can be used for both the A/D and the D/A converter to achieve maximum linearity and low power consumption. A 5th-order single-loop architecture has been used to implement a 14-bit 2.4 Msample/s A/D converter in the same 0.25 µm CMOS technology. The measured dynamic range is 86 dB while consuming only 50 mW of power.
A S?-topology has also been used to implement the customer premises D/A converter. A cascade of two stable 2nd-order S?-loops and a low oversampling ratio allows for a signal bandwidth of 4 MHz and a spurious-free dynamic range of 75 dB. This converter is being fabricated in an advanced 0.18 µm CMOS process.

Références bases de données (Anglais)

Swiss Database: Euro-DB of the
State Secretariat for Education and Research
Hallwylstrasse 4
CH-3003 Berne, Switzerland
Tel. [phone]
Swiss Project-Number: 98.0225