Partner und Internationale Organisationen
(Englisch)
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IMEC (Leuven, B); ST Microelectronics (Crolles, F); Institut für Integrierte Systeme (ETH Zürich, CH)
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Abstract
(Englisch)
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Downscaling of transistor technology (CMOS) has been the leading approach to address the performance issues of high-speed or low-power and/or low-voltage demands. The scaling of CMOS requires a reduction not only the effective channel, in order to decrease the carrier transit time from source to drain, but also a reduction of the the source-drain on-state voltage difference, in order to keep the effective lateral electric field of comparable intensity, so that device life time is not jeopardized. As a consequence, the integration of many CMOS devices into a circuit demand that the on-state gate voltage is comparable to the on-state source-drain voltage (VGS=VDS). The decreasing gate voltage has the important consequence that the insulating gate oxide also needs to be made thinner in order to provide a sufficient high transversal electric field in the channel for turning the transistor into inversion mode. The downscaling of the insulting layer is the key topic studied in the QUCUISS project.
Currently, operational devices are reported with oxide thickness of two nanometers. By limiting the oxide thickness to these small values there are several obstacles to surmount. First of all, the oxide reliability is questionable. Conduction paths are easily established because only a few electron traps in a stack are needed. Secondly, the ultra-thin oxides also lead to damage of the channel profile due to dopant diffusion from the poly above the gate insulator. Last but not least, quantum effects also are foreseen to effect the device behavior by direct leakage currents through the gate. Although this last effect may seem marginal for an isolated device, it becomes a serious problem when these devices are integrated into circuits. Therefore, the design community insists on strict upper bounds for the off-state leakage current of 10-9A/mm. Albeit, only a subset of all problems related to downscaling, the QUCUISS project was formulated to study the impact of quantum mechanical modifications on CMOS designs. In particular, the following fundamental question is addressed: At which point on the Silicon Roadmap do quantum-mechanical features begin to affect the electrical behavior in a significant way? Hence, the major goal of the QuCuiSS project was to determine how quantum mechanics is modifying the influence of the gate and the doping profiles on the charge distribution in inversion and accumulation channels of deep-sub micron MOSFETs.
In order to study this problem, numerical modules were developed that are capable of calculating quantum mechanically the spatial charge distribution in the conduction channel and exploiting the results to estimate the source-drain currents. The simulations of test structures containing various combinations of insulating layers (SiO2, Si3N4, and Ta2O5) performed with the numerical modules were used to formulate appropriate recommendations for future investigations of the dynamical features of quantum transport in advanced silicon MOSFETs. There have taken place three major parts of software development. At IMEC, the static self-consistent Poisson-Schrödinger solver SCALPEL was upgraded to account for finite barrier height as well as multi-dielectrics stacks. A similar upgrading was done for the DESSIS code at ETH and ISE. In particular, the inclusion of multi-layered insulator stacks required a serious code modification. The third major part of the developments was devoted to set up robust and flexible communication bridges between the newly developed modules and the state-of-the art software for device design DESSIS of ISE-AG. ISE-AG's tasks are focused on the following tasks: Specification of requirements, integration of the developed software into the ISE TCAD (Technology CAD) tools, simulations and studies on selected structures as well as dissemination of the software and application examples. Parts of the software, notably the developents in DESSIS, have been made available in ISE TCAD Release 6.0, which has been made available to customers in July 1999. The SCALPEL simulator, a number application examples for DESSIS and SCALPEL are available as add-on packages to ISE TCAD 6.0 and are accessible to interested parties since the end of the project, along with a collection of project deliverables and reports.
Among the recommendations for further investigations are: determination of material parameters for ultra-thin dielectrics as compared to bulk values, ab-initio calculations as molecular dynamics simulations, improvements of the quality of the silicon-dielectric interfaces, and a better understanding of the surface physics, e.g. by characterization of the interface states.
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