HIPADS: High-performance deep submicron CMOS analog-to-digital converters using low-noise logic

• Research unit: EU RFP
• Project number: 98.0170-1

Key words (English)

Mixed-mode design; low noise logic; A/D converters; microelectronic.

Alternative project number (English)

EU project number: 27917

Research programs (English)

EU-programme: 4. Frame Research Programme - 1.3 Telematic systems

Short description (English)

See abstract

Partners and International Organizations (English)

Mead Microelectronics SA (CH); ATMEL ES2 (F)

Abstract (English)

The aim of this project is to develop three different A/D Converters in deep submicron digital CMOS process, using a new Current Steering Logic (CSL) family approach that has the property of inducing a very low substrate noise. The converters are intended to become integrated components of larger systems, and should be considered presently as products under specs covering end user applications.
The trend of industrial demand for A/D converters is that of high performance in terms of resolution and speed at the same time, with the constraints of optimized power consumption and low supply voltage. In addition to the difficulty of such challenging analog design specifications, an A/D converter will be affected by all non-ideal effects inherently present in a mixed-signal circuit requiring fast and complex digital processing associated to a sensitive analog functionality. The parasitic coupling of the digital switching noise generated by the digital section of the circuit will be the limiting factor for the resolution. Moreover, this effect becomes increasingly restrictive in deep submicron technology.
In mixed-mode applications digital signal processing sections are usually implemented using conventional CMOS static logic, which is known to generate a large amount of switching noise. The existing methods used for reducing the effects of digital switching noise are mainly protective or defensive, such as shielding, symmetry and fully differential analog techniques.
In this project, in addition to these known techniques, an active method that decreases the parasitic coupling between analog and digital sections is proposed. Our choice is to use a new logic family, the CSL approach, whose characteristics make CSL very suitable for mixed-signal design.
The targets of this project are:
1. To develop a fully characterized Current Steering Logic (CSL) library as well as its design methodologies dedicated to mixed-signal industrial applications using a 0.35 mm digital CMOS technology.
2. To realize three A/D Converters for modern applications for audio codec, wireless communication systems, and video.
3. To compare CSL to standard static logic approach.

References in databases (English)

Swiss Database: Euro-DB of the
State Secretariat for Education and Research
Hallwylstrasse 4
CH-3003 Berne, Switzerland
Tel. [phone]
Swiss Project-Number: 98.0170-1