Objectives: The business objectives of the project are to reduce costly re-designs of smart power ICs due to substrate current induced failures, therefore to assure first silicon success and to improve time-to-market. The overall technical objective is to develop a design methodology that employs device and circuit simulation to assure IC functionality under current injection in the substrate. The design methodology will change from the current largely empirical approach to Computer-Aided Design guided critical parameter evaluation, validated by a relatively small number of measurements. More specifically the objectives are
1. to gain insight in substrate current distributions and to evaluate the crucial factors that determine its impact on possible malfunction of an IC.
2. to investigate and optimize substrate current barriers and other protective measures with respect to safe digital functionality and minimum area demands.
3. to provide rules for topology reduction in order to make numerical three dimensional device simulation of complex chips possible.
4. to deliver design rules that minimize deleterious substrate current effects for the IC designer.
Approach: The participating partners comprise the well-known system company R. Bosch GmbH, acting as the prime proposer, the TCAD softwarehouse ISE AG and the Integrated System Laboratory of the Swiss Federal Institute of Technology Zurich (ETHZ).
Bosch, as the industrial partner, specifies the technical problems, carries out the tasks, which are closely related to technology and validates the application of the methodology within an industrial environment. ETHZ systematically investigates the underlying coupling mechanisms, develops a topology reduction procedure and contributes with measurements by special facilities. ISE provides TCAD simulation support. This comprises the initial set-up of simulation examples for subsequent use and adaptation by the partners, the support of the partners during their TCAD activities, as well as the performance of simulations that go beyond the means of the other partners' expert knowledge and computing capabilities.
The project activities are split in 6 workpackages whereas ISE leads the workpackage '4. TCAD'.
Overall Summary (last reporting period):
The project has successfully completed the last reporting period.
The cooperation between the partners was very good. All milestones and project deliverables were written and delivered to the review team.
In this last reporting period the main project results were the following:
· In WP 2, remaining inconsistencies between measurements and simulation have been clarified. The methodology for characterizing substrate currents was described in the project deliverable 2.2.1
· In WP 3, the topology reduction methodology developed for the first testchip was successfully applied to the second smart-power technology. The results were summarized in the project deliverable 3.2.2.
· In WP 4, 2D transient simulations of simplified cross-sections were performed in order to understand the capacitive and diffusive coupling between the carrier injection sources in the power stages on the one hand and the logic part on the other hand. Several 3D transient simulations of the potential distribution on the full chip were performed and short movies of the changing potential distribution were generated.
· In WP 5, 2D transient simulations to study various protective measures were performed and guidelines for the chip optimization were formulated. The results were summarized in the two project deliverables 5.1.1 and 5.1.2.
Exploitation and information capturing & dissemination: The project consortium organised together with the ESD-MSD Cluster for Mixed-Signal Design a second workshop on substrate current effects, held during ESSDERC 2001 in Nuremberg, Germany. In addition, some main results were presented in a paper at ESSDERC 2001.
Furthermore, an article for the ISE NEWS 2001 was submitted. The ISE NEWS are published once a year and delivered to all customers.
A homepage about the SUBSAFE project has been designed by ISE AG. The address is
http://www.iis.ee.ethz.ch/nwp/subsafe/index.html
