Objectives: The business objectives of the project are to reduce costly re-designs of smart power ICs due to substrate current induced failures, therefore to assure first silicon success and to improve time-to-market. The overall technical objective is to develop a design methodology that employs device and circuit simulation to assure IC functionality under current injection in the substrate. The design methodology will change from the current largely empirical approach to Computer-Aided Design guided critical parameter evaluation, validated by a relatively small number of measurements. More specifically the objectives are
1. to gain insight in substrate current distributions and to evaluate the crucial factors that determine its impact on possible malfunction of an IC.
2. to investigate and optimize substrate current barriers and other protective measures with respect to safe digital functionality and minimum area demands.
3. to provide rules for topology reduction in order to make numerical three-dimensional device simulation of complex chips possible.
4. to deliver design rules that minimize deleterious substrate current effects for the IC designer.
Approach: The participating partners comprise the well-known system company R. Bosch GmbH, acting as the prime proposer, the TCAD software house ISE AG and the Integrated System Laboratory of the Swiss Federal Institute of Technology Zurich (ETHZ).
Bosch, as the industrial partner, specifies the technical problems, carries out the tasks, which are closely related to technology and validates the application of the methodology within an industrial environment. ETHZ systematically investigates the underlying coupling mechanisms, develops a topology reduction methodology and contributes with measurements by special facilities. ISE provides TCAD simulation support. This comprises the initial set-up of simulation examples for subsequent use and adaptation by the partners, the support of the partners during their TCAD activities, as well as the performance of simulations that go beyond the means of the other partners' expert knowledge and computing capabilities.
The project activities are split in 6 workpackages whereas ETHZ leads the workpackages '2. Characterization' and '3. Topology Reduction'. Work done in these two workpackages in the second project year is reported in the following.
Work progress
Characterization: A large number of transient measurements at various bias conditions have been performed. Namely, full H-bridge measurements of the transient below-ground and above-supply conditions on both testchips in BCD3s and BCD5 technology. Furthermore, measurements of the positive potential shift due to transient injected majority carriers (holes) under various bias conditions/temperatures were conducted on the second testchip in BCD5. Collection of transient injected minority carriers (electrons) by a logic n-well has also been measured under various bias conditions/temperatures on the second testchip. Minority carrier collection has been measured statically, too.
Influence of static and transient injected minority (electrons) and majority (holes) carriers on a CMOS-inverter has been investigated on the second testchip. No influence has been found.
Collection of transient injected minority carriers (electrons) has been simulated and compared to measurements. The good agreement (within a factor of 3) between simulation results and measurements validate the TCAD calibration. The results have been presented at ESSDERC 2001 conference.
Collection of transient injected minority carriers (electrons) has been simulated in 3D and compared to measurements. The good agreement (within a factor of 2) between full-chip 3D simulation results and measurements validate the TCAD calibration procedure and the topology reduction methodology. (3D simulations are still not state of the art today and an agreement within a factor of 2 for full-chip 3D simulations is considered good, therefore, and allows deriving important design decisions.)
The final workpackage 2 deliverable, 2.2.1 'Methodology for Characterizing Substrate Currents' has been written under the guidance of ETHZ. With this activity all due deliverables have been fulfilled and the workpackage has been successfully completed.
Topology Reduction: The topology reduction methodology for power stages, developed on testchip 1 in BCD3s Smart Power technology, has been applied to testchip 2 in BCD5 and has proven its validity by good agreement between simulation results and measurements. Thus, the methodology is validated for both technologies.
In the reporting period, the calibration of the simulation tool to the BCD5 Smart Power technology of the second testchip has been finished. The calibration procedure includes simulations, to which the topology reduction methodology, developed on BCD3s technology, has been applied. The topology reduction methodology has also been applied to simulations of the collection of transient injected substrate currents. Comparison with measurements shows a good agreement, which validates the topology reduction methodology. The simulations and measurements have been presented at ESSDERC 2001 as oral presentation.
A topology reduction methodology of the controlling circuitry (logic devices) of smart-power ICs has been developed in the reporting period. The topology reduction for logic devices has been applied to simulations of the collection of transient injected minority carriers. The good agreement between the full structure and the simplified structure validates the topology reduction methodology.
The final workpackage 3 deliverable, 3.2.2 'Topology Reduction Suitable to Simulate Substrate Current Induced Failures' has been written by ETHZ. With this activity all due deliverables have been fulfilled and the workpackage has been successfully completed.
Exploitation and information capturing & dissemination: The project consortium organized together with the ESD-MSD Cluster for Mixed-Signal Design the second workshop on substrate current effects, held during ESSDERC 2001 in Nuremberg, Germany. About 20 participants from European microelectronic industry and academia joined the workshop with major contributions from each project partner. The subject of one ETHZ presentation at the workshop was 'Transient simulations'. This presentation showed how to successfully conduct transient simulations that reflect critical operating conditions, gave insights into substrate coupling and stated recommendations to reduce coupling. The second presentation 'Measurements and Calibration' held by an ETHZ member gave an overview over measurement techniques and the simulation tool calibration procedure.
The paper entitled 'Transient Minority Carrier Collection from the Substrate in Smart Power Design' which has been prepared under the guidance of ETHZ has been presented orally at ESSDERC 2001 in Nuremberg (Germany). Several discussions after the presentation have shown that the project results are accepted and of interest to the Smart-Power community. The research group from LAAS-CNRS (Toulouse, France) led by G. Charitat has been identified which investigates the same subject.
An extended and revised paper entitled 'Substrate Potential Shift due to Parasitic Minority Carrier Injection in Smart Power ICs: Measurements and Full-Chip 3D Device Simulation' has been published in the June release of the 'Microelectronics Reliability'. The paper has been prepared under ETHZ's guidance.
A paper entitled 'TCAD based Design Methodology for Substrate Current Control in Smart Power ICs' has been prepared under the guidance of ETHZ and has been submitted to ISPSD 2002 conference.
The homepage about the SUBSAFE project is update periodically. The address is
http://www.iis.ee.ethz.ch/nwp/subsafe/index.htmlBosch is doing the industrial exploitation by introducing the validated design methodology into the industrial design process.
