MELOPAS: Meter low power ASIC

• Research unit: EU RFP
• Project number: 98.0055-2

Key words (English)

Low power ASIC; simulator mixed-mode systems; power consumption

Alternative project number (English)

EU project number: 29564

Research programs (English)

EU-programme: 4. Frame Research Programme - 1.3 Telematic systems

Short description (English)

See abstract

Partners and International Organizations (English)

Coordinator: Schlumberger (F)

Abstract (English)

Most of the tools developed in this project have been successfully integrated in CooIRIDE, the CooIRISC Integrated software Development Environment. The integration simplifies their operation by providing a user-friendly graphical interface and a unified development environment.
The main objective of this project is to complete simulation mixed-mode systems on a chip (SoC) at the behavioral and/or RTL levels. The targeted SoC contain a very low-power 8-bit microprocessor (mP) core (CooIRISC 816), low-power memories, as well as analogue and digital modules (peripherals, oscillators, power-on-reset, etc). The hardware modules described in VHDL/Verilog are simulated using a commercially available simulator, and the CooIRISC embedded software with a software debugger that includes an instruction-level software simulator.

A second objective is to allow a power consumption estimation of the entire SoC. Power consumption data is gathered during the co-simulation. It includes data from the processor instruction execution, the various memory accesses and from the power consumption modeled VHDL/Verilog modules. The hierarchical visualisation of the evolution of the power consumption over time is intrinsically made available by this methodology and tools.

A third objective is to provide an easy and time-efficient way to specify and to code in VHDL (by calls to a specifically developed power consumption tracing library) the power consumption model of any hardware module, either analogue or digital. Power consumption contributions can be specified as energy contributions in Joules or as power contributions in Watts. The latter implies an integration of the power over time. Power contributions are appended to the trace file. Values can be specified as numerical value, or as symbolic expressions. In order to speed-up the co-simulation, the power consumption models for the microprocessor and its memories have been implemented in the profiler's power consumption visualization tool. These models use an average energy per access for memories, and an average energy per kind of instruction executed for the microprocessor.

The last but not least objective of these tools is to allow CooIRISC program execution profiling. The profiling helps software designers to optimize programs that are to be run by the SoC, by allowing the designer to determine which are the routines that are the most invoked and which routines are executed most of the time. This optimization can ultimately result in a faster program execution and a reduction of the power consumption.

References in databases (English)

Swiss Database: Euro-DB of the
State Secretariat for Education and Research
Hallwylstrasse 4
CH-3003 Berne, Switzerland
Tel. [phone]
Swiss Project-Number: 98.0055-2