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Unité de recherche
PCRD EU
Numéro de projet
98.0055-1
Titre du projet
MELOPAS: Meter low power ASIC
Titre du projet anglais
MELOPAS: Meter low power ASIC

Textes relatifs à ce projet

 AllemandFrançaisItalienAnglais
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Références bases de données
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Textes saisis


CatégorieTexte
Mots-clé
(Anglais)
High-level design methodology; hardware/software co-simulation;
power estimation tool; low-power mixed-signal asic development
Autre Numéro de projet
(Anglais)
EU project number: 29564
Programme de recherche
(Anglais)
EU-programme: 4. Frame Research Programme - 1.3 Telematic systems
Description succincte
(Anglais)
See abstract
Partenaires et organisations internationales
(Anglais)
CSEM (Neuchatel, CH); Slumberger (Macon, F)
Résumé des résultats (Abstract)
(Anglais)
MELOPAS ' objective was to develop and test a methodology and tools that guarantee from system level analysis that low-power mixed mode signal ASICs with embedded microprocessors can match their target power consumption specifications.
The partners Schlumberger, XEMICS, and CSEM worked on the appropriate modeling languages, design flow and simulation tools to evaluate the power consumption of mixed-signal ASICs during system simulations. Then this methodology was validated through the design of an ASIC that includes an 8-bit microprocessor core, embedded program and data memories, digital peripherals, an LCD driver, and a high-resolution data acquisition function.
Within this program, XEMICS contribution focused on the IC design methodology that allow power consumption analysis during the early stages of the project, and on the validation of this methodology throughout the design of a custom mixed signal ASIC for residential heat meters. This project was divided into 3 major phases: 1) System Architecture during which the detailed architecture of the ASIC and the product were defined; 2) Hardware and Software development during which the actual design of both hardware and software took place; and 3) Firmware power optimization during which the firmware detailed scheduling of was optimized to match the power consumption target.
The MELOPAS co-simulation tool was used to validate the hardware and software design and to optimize the power consumption of the ASIC, where they helped to highlight large power consumer and to converge to a global minimum in terms of system power consumption.
Thanks to extensive use of the developed tools, the first ASIC samples were almost fully functional, with excellent metrology performances. This is a major success, as this ASIC has more than one million transistors between the sophisticated analog function and the digital building blocks. The main drawback has been the speed of the co-simulation process where one need 15s of CPU time to simulate 1ms of real time. In spite of this, the power analysis tool and the co-simulator tool are operational and XEMICS can benefit from the results obtained here for other programs.
Project results were disseminated according to UE program rules at the ESDLPD'00 workshop (Italy: Rapallo, 25 to 28 July 2000), a major event for the Low Power Design Initiative. The MELOPAS synthetic objectives & results, the end product and its previous generation were presented at IST (France: Nice, November 5-8, 2000)
Références bases de données
(Anglais)
Swiss Database: Euro-DB of the
State Secretariat for Education and Research
Hallwylstrasse 4
CH-3003 Berne, Switzerland
Tel. +41 31 322 74 82
Swiss Project-Number: 98.0055-1