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Unité de recherche
PCRD EU
Numéro de projet
97.0390-2
Titre du projet
ADAMO: Adaptive antennas in mobile terminals for wireless broadband communications
Titre du projet anglais
ADAMO: Adaptive antennas in mobile terminals for wireless broadband communications

Textes relatifs à ce projet

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Mots-clé
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Description succincte
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Références bases de données
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Textes saisis


CatégorieTexte
Mots-clé
(Anglais)
Adaptive Antennas; Hybrid Analog-Digital 'Beamforming'; Low Power HIPERLAN Terminals; Wireless Broadband Communications.
Autre Numéro de projet
(Anglais)
EU project number: 27001
Programme de recherche
(Anglais)
EU-programme: 4. Frame Research Programme - 1.3 Telematic systems
Description succincte
(Anglais)
See abstract
Partenaires et organisations internationales
(Anglais)
Coordinator: Thomson-CSF Communications (F)
Résumé des résultats (Abstract)
(Anglais)
The objective of the ESPRIT project ADAMO (ADaptive Antenna for MObiles) is to validate the potential of simple (i.e., low cost) adaptive antennas for improving the performance and reducing the power consumption of HIPERLAN (ETSI standard for high speed wireless LANs) modems. Instead of employing a complex, high speed (e.g., 47 MSamples/s) adaptive equalizer (i.e., a digital transversal filter) to mitigate the detrimental effects of intersymbol interference caused by multipath propagation, spatial filtering is applied by appropriately weighting and combining the RF signals coming from three independent antennas. Since this 'beamforming network' is realized with analog circuitry (i.e., phase shifters and amplifiers) power dissipation can be reduced considerably relative to a solution based on a digital equalizer. IIS's contribution consists of implementing the digital signal processing required to compute the combiner coefficents of the adaptive antenna in a dedicated ASIC called the AdAnTE (Adaptive Antenna Training Engine) chip. Due to the fact that this processor is only active during the training header of each data packet to compute the new weights and set idle when actual information transmission takes place, the current consumption owing to high speed digital switching is minimized. The main part of the AdAnTE datapath consists of a linear systolic array of pipelined CORDIC (COordinate Rotation DIgital Computer) processor elements, leading to a highly modular, readily extendable VLSI architecture.
Références bases de données
(Anglais)
Swiss Database: Euro-DB of the
State Secretariat for Education and Research
Hallwylstrasse 4
CH-3003 Berne, Switzerland
Tel. +41 31 322 74 82
Swiss Project-Number: 97.0390-2