Résumé des résultats (Abstract)
(Anglais)
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Introduction
- Purpose of the LAYIN Tool Suite
Perturbations generated by the noisy parts of an integrated circuit (IC) affect sensitive sections through both routing lines and substrate. In the past, these perturbations could safely be neglected. Since a few years, this is no more the case: first, higher levels of integration allow to integrate on the same chip analog and digital functions; second, operating frequencies are very high and reach radio frequencies; and third, device sizes are well under the micron. For these three reasons, IC designers and especially mixed-mode and analog IC designers have to take account of interconnect and substrate coupling.
This project aims at providing an industrial computer software to semiconductor companies. Starting from a functional netlist, from the IC layout and from a description of the technology, the software extracts the parasitic substrate model of the IC, completes the simulation data files, and displays the substrate noise distribution. It also includes a parameterization tool to create technology descriptions from actual fabrication process data.
- Reminder of Project Objectives
The main goal of this project is to provide to IC designers a complete, simple-to-use industrial software tool that models and analyses the parasitic substrate effects in integrated circuits, and allow to take account of these effects into the simulation of the IC.
- Framework
This project involves two consortium. The users are the initiator of this project. Their task is to evaluate an existing prototype to provide feedback to setup the final product specification, as well as to test and illustrate the tool usage in an industrial environment. The providers are in charge of setting up the first prototype version and to develop the final software in accordance with the specification required by the users.
- Achievements
The project has been realized according to the plans. All users have been delivered several intermediate Layin beta releases, sometimes with some advance on the plans. All planned specification items have been implemented, and several additional features, that were asked for by users in the middle of the project, have been added.
Layin V2.0 has been released in December 1998, on schedule, and fully complies with the specifications produced by the partner consortium.
A high level of support has been given to all users throughout the whole project, by phone, email, and through many visits on customer sites. At each intermediate release, users have received a personalized training on the new features.
All users have actively contributed to define the final product specifications. Thanks to the wide range of expertise provided by the users, the tool has been dramatically improved together with the usage methodology.
For all those reasons, we consider this project as a success.
Contribution of users
The user consortium includes 5 partners: ATMEL, CISS, ERICSSON, MITEL and STMicroelectronics. The feedback provided by the users is specific to the structure and expertise of each of the partners. Owing to the complementary contributions, Layin v2.0 has been tested with different fabrication processes - pure CMOS, pure bipolar and BiCMOS - as well as for different applications - RF, I/O structures and CODEC.
- ATMEL
Layin was used by analog designers in the wireless design group of ATMEL to build analog layout guidelines for mixed mode designs. Matching of transistors, shielding of resistors, efficiency of noise isolation with p+ substrate, better characterization of ESD protection were chosen as subjects for investigation. The process was a digital 0.5um CMOS, p+ substrate. The fabrication process is pure CMOS. The CADENCE plug-in version of Layin is used allowing the automatic generation of 'mixed' netlist from layout views.
Four layout configurations were classified in terms of sensitivity to DC and AC currents in the substrate. Layin was used to perform the 'substrate components' extraction. This work was chosen to demonstrate the efficiency of the Layin extractor. The simulated results obtained are similar to measurements (same classification). The good behaviour of the extractor is thus verified.
- CISS
The different intermediate releases have been evaluated to report GUI bugs and discrepancy between the software and its documentation. CISS has been checking the full concordance of Layin v2.0 graphical user interface (GUI) with the final specifications. Owing to the comments reported by CISS engineers, the final version of Layin product can easily be installed and operated by an end-user, with reduced support from Snaketech.
- ERICSSON
Ericsson is using Layin to evaluate signal integrity degradation due to substrate disturbance and interconnect cross-talk for one-chip mixed analog-digital sub-blocks in wireless communication systems. They are using a BiCMOS technology.
The usage includes LayinTCT to extract a description of their technology, as well as the CADENCE plug-in LayinCDS. Ericsson joined the project for the last six month and didn't participate to the specifications. However, they provided many tips and suggestions to improve the software ease-of-use.
Two circuits have been simulated with Layin substrate model. As a result, with their technology, it appears that the main mechanism for substrate noise injection happens through the power supply contacts. Layin model has proven to be a vital part in a complete model of the whole integrated circuit and Ericsson continues to use Layin for new IC projects where substrate modeling is required.
- MITEL
With the only pure bipolar process, MITEL provided critical information to improve the technology characterization tool, LayinTCT. The complexity of the high-speed bipolar process has greatly contributed to the improvement of the TCT and to its final stability. Thanks to the work done at MITEL, the characterization of BiCMOS technologies at ERICSSON and STMicroelectronics has been greatly simplified.
- STMicroelectronics
Several test structures were designed early in the project in order to evaluate Layin, and possibly alternate solutions. Evaluation has been more specifically oriented toward RF applications. For this reason, all test structures are implemented in BiCMOS-6 technology. Two structures are pure measurement structures. The third structure is a Low Noise Amplifier Cell designed for RF applications.
It appears from the two measurement structures that the accuracy of Layin substrate model is excellent. Additionally, the RF group has illustrated several practical examples as to how Layin can help device and library characterization.
Contribution of providers
Providers include EPFL and Snaketech. The first has developed the original technology that has been implemented as part of the prototype. During the course of this project, the technology has been successfully transferred to Snaketech.
- EPFL
The technology implemented in Layin is provided by EPFL. The initial prototype has been transferred to Snaketech. EPFL joined Snaketech to deliver the first prototypes as well as to train the end-users. The expertise of EPFL in substrate effects has also been critical to define the final product specifications as well as to direct the task of Snaketech development team. EPFL participated to the edition of the support materials - manuals, courses, presentations. Additionally, the new features have been prototyped by EPFL as part of several research projects including kernel improvement, Cadence encapsulation, netlist connection, technology characterization.
- Snaketech
The role of Snaketech is central as product provider and project manager. The initial technology from EPFL has been turned into an industrial package including the software together with documentation - reference and user manuals, tutorial - and courses. New engineers have been hired to provide Layin-specific support to end-users. Following the success of this project and the increasing interest of users, Snaketech has already started the dissemination. Besides, the excellent cooperation with EPFL will be carried on to increase further the efficiency of the Layin technology.
Conclusion
All partners have actively contributed to define the final product specifications. Thanks to the wide range of expertise provided by the users together with the providers, the tool has been dramatically improved together with the usage methodology.
Layin v2.0 is now distributed and supported by Snaketech. EPFL is starting new research projects involving Layin to take care of substrate modeling. The five users involved in the project committed already to continue using the tools to solve substrate-related troubles.
Two new customers recently purchased the Layin. Four additional companies are currently evaluating Layin inside their design flow and the industry interest into Layin is starting to grow rapidly.
For all those reasons, we consider this project as a success.
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