ESCHETA: Development of European CSP sources for harsh environment, telecom and automotive

• Unité de recherche: PCRD EU
• Numéro de projet: 97.0266
• Titre du projet anglais: ESCHETA: Development of European CSP sources for harsh environment, telecom and automotive

Mots-clé (Anglais)

Chip scale package; wafer level CSP; flip chip; solder bump; PAD redistribution

Autre Numéro de projet (Anglais)

EU project number: 26.245

Programme de recherche (Anglais)

EU-programme: 4. Frame Research Programme - 1.3 Telematic systems

Description succincte (Anglais)

See abstract

Partenaires et organisations internationales (Anglais)

Alcatel SEL AG (D), Bull SA (F), Sorep-Erulec SA (F), Matra BAe Dynamics (F), Infineon AG (D), Siemens Automotive SA (F), Technische Universität Berlin (D), Pac Tech GmbH (D)

Résumé des résultats (Abstract) (Anglais)

The technical objectives of this project are:
· to develop and establish various Chip scale Packages (CSP) which will be provided by European sources. These innovative developments will be based on the different types of redistribution such as wafer level (named CSP I), flexible interposer in fan-out configuration (CSP II) and rigid interposer plus flip chip attach (CSP III).
· to qualify the CSPs for usage under telecom and harsh environmental conditions.
· to validate the feasibility and manufacturability in a standard SMT process by setting up the fully functional demonstrators for an automotive control unit (ACU) and a telecom switching (high power) application.
The main contribution of EM Marin is in the industrialisation of CSP I, a wafer-level type package.
The process for this wafer level CSP with solder support structure (S3-Diepack) has been successfully transferred from Technical University of Berlin, EM's direct partner in this project. In addition to the basic process steps, higher level industrial processes to deposit the solder support structure and the solder balls have been evaluated and demonstrated during the duration of this project.
The Diepack process allows the fabrication of chip scale package at wafer level with favourable cost structure allowing for the manufacturing of such devices in Europe. It is based on a process for solder bump technology for flip chip (DCA). In an expansion of the solder bump process the under bump metallisation (UBM) serves as redistribution layer to reroute peripheral pads to an area array. Different process options can be incorporated from simple pad redistribution to the complete Diepack process including solder balls and solder support structure.
The results of the work in this project have been presented at international conferences:
The modular approach of the process has been presented at IEMT Europe Symposium (Munich, April 00): 'From Direct Chip Attach to Wafer Level CSP'.
Key results on process, cost structure and reliability have been presented at 13th European Microelectronics and Packaging Conference (Strasbourg, May 01): 'Wafer Level CSP with Solder Support Structure'.
The exploitation plan shows a strong growth of wafer level CSP for the next years.

Références bases de données (Anglais)

Swiss Database: Euro-DB of the
State Secretariat for Education and Research
Hallwylstrasse 4
CH-3003 Berne, Switzerland
Tel. [phone]
Swiss Project-Number: 97.0266