LISCOM: Listening comfort system for hearing instruments and telephones

• Forschungsstelle: EU FRP
• Projektnummer: 96.0383-1
• Projekttitel Englisch: LISCOM: Listening comfort system for hearing instruments and telephones

Schlüsselwörter (Englisch)

Noise reduction technique; hearing impaired peoples; low-power design methodology

Alternative Projektnummern (Englisch)

EU project number: DE 3005

Forschungsprogramme (Englisch)

EU-programme: 4. Frame Research Programme - 1.1 Information technologies

Kurzbeschreibung (Englisch)

See abstract

Weitere Hinweise und Angaben (Englisch)

Full name of research-institution/enterprise:
Université de Neuchâtel
Institut de Microtechnique
Laboratoire d'Electronique et de Traitement du signal

Partner und Internationale Organisationen (Englisch)

Cooerdinator: Agora Conseil (F); CH: Phonak AG

Abstract (Englisch)

Noise reduction technology applied to hearing impairment requires frequency dependent signal analysis such as NSS in order to identify whether it is speech or noise. Thus, in any digital hearing aid algorithm, one can find the basic function, the so-called Fast Fourrier Transform (FFT). FFT algorithm require an important computational load because the time-to-frequency and frequency-to-time conversions have to be done in real time; this represent almost 50% of the computational load, and most power consumption is related to this computation.
By introducing a new FFT and IFFT co-processor concept instead of using a standard DSP for FFT computation, the project wishes to reduce the number of cycle for FFT and IFFT computation while keeping a solid frequency resolution and an acceptable I/O delay. The dedicated architecture of this FFT co-processor allows reducing the consumption of the whole system in order to fit the system to hearing aid market. The co-processor could work together with a flexible DSP processor, which is responsible for NSS algorithm.
Complexity reduction researches led to the choice of an optimized implementation, which includes:
- A 128-FFT transform, with an 87.5 overlap factor, reduce the I/O delay to hearing aid requirements. The frequency resolution is 125 Hz with a sampling rate of 16 kHz.
- A delay reduction down to 6 ms at a system clock frequency of 3.75 MHz. This frequency corresponds to the range of frequency used by digital system in the hearing aid market. The obtained delay is quite acceptable compared with hearing aid market standards.
By using a C32 of Texas Instrument (30 MIPS), this implementation for the co-processor leaves a total amount of more than 10000 cycles to the DSP for NSS computation.
A platform demonstrator has been developed in order to validate the above solution. This demonstrator is a 15X20 cm Printed Circuit Board (PCB), including 2 Field Programmed Gate Array (FPGA), 4 RAM memories and a CODEC. The DSP, the C32 of Texas Instrument is used in a PCM-CIA card, called Bullet II, and is linked to the PCB through a serial port. A C-program controls this DSP. The CODEC is the AD73322 of Analog Devices. The two-used FPGA are from Gatefield Inc. One is responsible for the input-output process (IOP), which stores the data out of the CODEC in a form that is usable for the co-processor. It is also responsible for the control of the serial port between the PCB and the DSP and all communication between the FFT co-processor and the DSP. The second FPGA contains the FFT co-processor itself.

Datenbankreferenzen (Englisch)

Swiss Database: Euro-DB of the
State Secretariat for Education and Research
Hallwylstrasse 4
CH-3003 Berne, Switzerland
Tel. [phone]
Swiss Project-Number: 96.0383-1