Partner und Internationale Organisationen
(Englisch)
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IRobert Bosch, Reutlingen (D)
IMEC, Leuven (B), ISE AG, Zürich (CH), SGS Thomson, Cornaredo (I), Universität Bologna (I)
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Abstract
(Englisch)
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The ambitious goals of the project, the development and verification of a methodology for ESD (Eletrostatic Discharge) protection, have been reached. More specifically, a simulation guided design methodology based on TCAD (Technology CAD) and on circuit simulation was developed and has been validated for different technologies, namely the BCD3 smart power process of ST-Microelectronics/Bosch and the half and quarter micron VLSI and ULSI processes of IMEC. According to technical standard and market requirements emphasis of the investigations was put on Human Body Model (HBM) type ESD stress, in addition Charged Device Model (CDM) stress has been investigated.
TCAD proved to be indispensable to gain physically based insight into ESD problems. This physical understanding was impressively employed for TCAD guided device and Process optimization. Thus TCAD is necessary for well targeted test structure design. Although structure design success is significantly accelerated by TCAD, test structures are still needed for calibration, validation of new device classes and the evaluation of 3D effects such as inhomogeneous triggering in devices with complex structures.
As a link between TCAD and circuit models an interface was created to enable parameter extraction from TCAD simulations. A modular ESD sub-circuit model has been developed for the flexible modeling of the high current behavior of bipolar or of MOS transistors including gate coupling. The ESD-MOS model was successfully validated on several critical circuits. The results of the application examples underlined that circuit simulation is a powerful tool to optimize protection schemes and to avoid design errors.
Basic physical models that had been lacking and which are relevant for ESD modeling have been provided, validated by industrial partners, and commercialized by ISE AG.
Exploitation of the scientific and technical results
A considerable amount of work was spent by ETHZ and ISE to organize and hold the ESPRIT ESDEM Public Workshop 'ESD Protection Design Methodology'. It took place very successfully on Feb. 15 1999, within the framework of the international EMC'99 Symposium at ETH Zürich.
ISE AG began to implement the feedback from the exploitation of the software provided during the precedent periods, where a first version of the parameter extraction tool had been delivered with ISE TCAD Release 5.0 in the first half of 1998 to the partners. This feedback enabled ISE AG to redesign the simulation interface to the industrial standards ICCAP (HP) and UTMOST (SILVACO).
The first feedback from PAREX clients turned out that PAREX is not easy to handle because in most cases device-simulation specialists do not know how to use ICCAP and measurement specialists do not know how to perform device simulation.
Therefore, procedures have been developed in Tcl (Tool Command Language) that easily allow printing simulated values in a format that is readable for ICCAP or UTMOST. This task is performed with the curve visualization and extraction tool INSPECT-ISE and hence does not directly influence the preceding device simulation set-up. This customization does not require the modification of PAREX or the implementation of a new tool. Instead, the developed software is an integral part of the GENESISe application project setup (GENESISe is the user interface of ISE TCAD system). These projects implement to a large extent the know-how gained from simulation; versions of the projects without confidential data will be made available to customers in form of documented application examples. These examples are typically modified by customers to suit their specific needs.
First tests done by Bosch confirm the usability of the new utilities to transfer simulation output to third party software.
A large number of tests of all the new features implemented in release 6 of ISE TCAD software have been effected and show progress in user friendliness of the software package. These test cover especially the new Uni Bologna high temperature models, the facilities to recover layout data by the layout editor PROLYT-ISE and the transfer of simulation results to circuit simulators.
The official ISE TCAD Release 6.0 has been distributed by the end of July 1999.
Generation of compact circuit models from large layout
A central question concerning the LDMOS used as ESD device is to understand mechanisms of the inhomogeneous triggering of devices with complex structures. As a first approach, the solution of the Poisson equation for a 3D model was assumed to lead to significant inhomogenieties of the electrical field distribution and hence of the impact ionization. Creation and debugging of the 3D model was time-consuming, but successful.
Because the solution of the Poisson equation did not yield the desired results, the fully coupled three equations (Poisson, electron, holes) were solved in a DC simulation. Inhomogeneous distribution of the hole current and electron current could clearly been seen, however, the snap-back could not be simulated this way. The main reason was found in the too coarse grid (25'000 vertices).
A simulation with a finer grid (45'000 vertices) still showed convergence problems in the region of an inner drain voltage of 50 V. Finally, a transient TLP simulation could be completed successfully. The snap-back behaviour could be reproduced. Inhomogeneieties in the triggering could be observed.
In addition, the calibration of the LDMOS transistor was completed. It was a prerequisite for further more precise simulations run by ISE AG, Bosch, and ETHZ. Using the ESDPBLAT and the LDMOS protection devices, transient thermo-electrical simulations were run with different thermal boundary conditions to investigate the influence of thermal coupling. In addition, a 5V NMOS transistor has been simulated using different current slopes for the extraction of the base transit time. Finally ETHZ investigated the triggering behavior of a multi-finger LDMOS transistor with an inner and an outer finger. Reasons for a non-uniform current distribution between inner and outer fingers could have been seen and demonstrated.
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