Partner und Internationale Organisationen
(Englisch)
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CNM-CSIC (E), Detexis Thomson-CSF (former Dassault Electronique, F), Dicryl (E), D+T (E), NMRC (IRL); SIBET (D), 1N2P3-LNPHE (F), ETH Zürich (CH)
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Abstract
(Englisch)
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The target of the project is to establish a solid industrial basis to be able to exploit deeply the technology of MCMs with Smart Substrates and Ball Grid Array (BGA) Connection. The Smart Substrate, next to the MCM-D (thin-film) typical high-density interconnects offers the possibility to integrate passive components as well as active circuitry. The advantage is to spare surface mounting of passive components or small ICs and/or glue logic. Thus, the substrate is not only a physical support and interconnection for chips and components, but also provides functionality that is always needed around standard chips.
Achievements:
The Smart Substrate technology and assembly capabilities have been set up successfully at CNM and Dicryl. A library of integrated passives and active structures has been developed, tested and transferred to the partners. A Data Acquisition Chain demonstrator using active substrate technology has been manufactured and tested.
Swiss Contribution:
In this project, ETH Zürich took part in Workpackage 5 (Demonstrators) contributing the cost accounting of demonstrators and processes. This task has been two-fold: on the one hand, the cost structures of the partners had to be analyzed in order to predict the costs of the demonstrators to be produced. On the other hand, based on the knowledge gained, different technical solutions were evaluated to ensure a cost-effective design and production of the proposed demonstrators. For the second part, a generic cost optimization tool has been developed allowing the fast cost assessment of alternative solutions.
Based on fabrication models developed for the partners' process lines, ETH has completed the cost assessment of demonstrators and fabrication lines. Whereas the SUMMIT assembly process is well in the range of competing companies, the cost of the MCM-D substrate is still ten times the cost of an advanced printed circuit board (PCB). This cost penalty is caused by the small substrates (up to 5' wafers) compared to panel sizes of 24' x 24' inch2 for PCBs. This problem is currently being addressed in the follow-up Esprit project 26261, LAP (Large Area Panel Processing).
Cost calculations for the demonstrators were conducted. For the first demonstrator, using integrated passives, we compared different implementation strategies. The results revealed that an implementation where integrated passives replaced the SMDs only when consuming less area and ensuring the specifications is most favorable. This solution offers the highest size reduction (-60% compared to a Printed Circuit Board), on the expense on a small 10% cost penalty. For the second demonstrator, using active substrate, cost calculations showed clearly that a very high utilization of the expensive active substrate area is mandatory in order to achieve cost effectiveness.
Benefits:
The cooperation in the SUMMIT consortium enabled the ETH-IfE to extend its competence in the field of cost modeling. Due to the strong relations to the industry partners, our laboratory gained valuable insight into confidential cost data, allowing to improve and to test our methodology. The partners benefited from the 'neutral', non-competitive position, giving the opportunity for a fair cost benchmark and analysis.
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