ATLANTIC: Advanced television at low bit rates and networked transmission over integrated communication systems

• Research unit: EU RFP
• Project number: 95.0741

Key words (English)

MPEG2 over broadcast networks; video compression; motion estimation; VLSI; MIMD architecture; genetic algorithms

Alternative project number (English)

EU project number: AC078

Research programs (English)

EU-programme: 4. Frame Research Programme - 1.2 Communications technologies

Short description (English)

See abstract

Further information (English)

Full name of research-institution/enterprise:
EPF Lausanne
Laboratoire de traitement des signaux
STI/ITS/LTS3 ELB 120

Partners and International Organizations (English)

BBC (UK), Snell&Wilcox (UK), ENST (F), CSELT (I), IENSC (P), FhG (D)

Abstract (English)

The ATLANTIC project concentrated mainly on aspects related to the assembly, transmission and final distribution of MPEG2 signals with the focus of providing equipment for a high-profile final demonstrator. The project's goal was to demonstrate a significant number of the necessary elements of a broadcast, multimedia and information service which is based entirely on the MPEG2 coding standard. The Integrated Systems Center (C31) of the EPFL participated within this project as one of the main developers of second generation VLSI for a MPEG2 encoder, a key outcome of this project, using advanced motion estimation and coding technology developed in previous RACE II projects (e.g. COUGAR).

As a joint work between the C31 and the CSELT telecommunication research laboratories in Torino/Italy, and in close co-operation with the BBC R&D laboratories and the British video hardware manufacturer Snell&Willcox, a new, versatile motion estimation chip has been developed- the so-called IAMGE chip (Integrated MIMD Architecture for Genetic Motion Estimation). This has been achieved under special consideration of concurrently developed video encoder hardware for broadcast studio environments which uses a new approach for minimizing cascading impairments.

The chip implements an unconventional, high performance motion estimation algorithm which is based on tracking motion through several frames and on a genetic search strategy. The component is capable of performing a variety of different motion estimation related tasks and offers a variety of optional enhancements to optimize the final coding quality to a max. This tunctionality has been mapped into a MIMD based parallel architecture. All algorithms are executed on embedded RISC controllers which provides a high flexibility. Several strategies for multi-chip configurations allow increase the coding quality according to system needs. The chip has been integrated in a modern O.35um 5-metal-layer CMOS technology on an area of 60 mm2. It contains approximately three million transistors and provides a peak processing power of about four billion operations per second. The chip has been fully layouted and is ready for fabrication.

Due to the manufacturer-specific interfaces, the chip is ready for the glueless incorporation in future high-quality video encoder boards. By changing this interface concept to a more generic one (e.g. by incorporating standard bus-interfaces like PCI), a motion estimation circuit for a broader range of video coding systems can be designed by reusing most of the designed blocks of the IMAGE architecture.

The chip concept is also very suitable for future video coding systems for high-resolution TV (HDTV). This extension of the architecture concept in this direction is subject of an ongoing PhD thesis.

References in databases (English)

Swiss Database: Euro-DB of the
State Secretariat for Education and Research
Hallwylstrasse 4
CH-3003 Berne, Switzerland
Tel. [phone]
Swiss Project-Number: 95.0741