IDSCAN: VHDL based processor and communication interface for RF identification scanners

• Forschungsstelle: EU FRP
• Projektnummer: 95.0646-1e
• Projekttitel Englisch: IDSCAN: VHDL based processor and communication interface for RF identification scanners

Schlüsselwörter (Englisch)

VHDL; scanners; mixed-signal IC design

Alternative Projektnummern (Englisch)

EU project number: 25.157

Forschungsprogramme (Englisch)

EU-programme: 4. Frame Research Programme - 1.3 Telematic systems

Kurzbeschreibung (Englisch)

See abstract

Partner und Internationale Organisationen (Englisch)

TTN Lausanne (EPFL)

Abstract (Englisch)

RF-ID system involves remotely energizing a passive transponder by means of a radio frequency filed. The transponder comprises and Integrated Circuit (IC) containing a unique identifying code which is connected to a coil. There is no power supply. When an RF field is applied from distance by a scanner, the transponder receives enough energy to operate and send its code back to the scanner.
One of MEAD's main activities consists of providing the market with low-power RF systems consisting of passive transponders as well as low-cost scanners. This can only be achieved by some level of component integration on both ends.
The objective of this experiment (ESPRIT- FUSE - First User project) can be summarized in three different parts of the project: a) improve design efficiency with new 'design methodology' by using VHDL, b) apply the new design methodology to MEAD's products and custom projects, in particular to low-power RF systems, and c) dissiminate the results with the goal to enable third party to look at MEAD's 'before and after' the experiment concerning the new methodology.
The first part of the project consisted of training MEAD's engineers on a new tool, VHDL, and to choose the vendor for our internal CAD configuration. Five different engineers have been trained and the VHDL tool is now regularly used in the company.
The objective of the second part of the project has been achieved by several technical realizations using the new methodology. Two reader chips (IC part of the scanners) and a 4-bit microcontroller have been designed during the period of this experiment. The first reader chip is a mixed-signal chip working at 125 kHz carrier frequency. The second reader chip is only analog with carrier frequency of 13.56 MHz. The 4-bit microcontroller core contains also 16 registers, a 4 x 256 bits RAM and 4k x 12bits ROM. All these chips were realized in 1um CMOS process.
The third and final part of the project consists presently in dissemination of the results of the experiment. This will comprise a special page on our web site (http://www.mead.ch), presentation of the experiments to companies interested in our new design methodology, and the contact with Innovation Relay Center (IRC) of West Switzerland.
The major benefit of the IDSCAN project has been the increase of competitiveness of our company due to the new design methodology. This has been already proven by newly obtained projects in the field of low-power RF systems and their respective technical realizations.

Datenbankreferenzen (Englisch)

Swiss Database: Euro-DB of the
State Secretariat for Education and Research
Hallwylstrasse 4
CH-3003 Berne, Switzerland
Tel. [phone]
Swiss Project-Number: 95.0646-1e