Abstract
(English)
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1. Objectives
Goal of Task 7 of the RAPSDRA project was the modelling of the failure rate of IGBT multichip modules which are operated in a realistic environment of a current converter for railway traction applications. The main focuses of present work have been both the investigation of the device end-of-life behavior and the investigation of the interactions between technology and expected lifetime of the devices.
The Task has been subdivided into four sub-tasks: Statistical Data Analysis, Physical Failure Rate Modeling, Thermomechanical Related Failure Mechanisms, and Failure Prediction at Converter Level. The status of each sub-task is summarized in Tab.1. The results of Task 7 have been presented to the project consortium during the final Task Meeting on October 22, 1998 in Zurich.
2. Completion Grade
Review of Reliability Simulators: delivered
Statistical Data Analysis: delivered
Physical Failure Rate Modeling delivered
Thermomechanical Related FM: delivered
Prediction at Converter Level: delivered
Failure Analysis Handbook: delivered
3. Status of the different sub-tasks
Initially Planned Activities vs. Work Actually Accomplished
The fact that the ETH Reliability Laboratory ceased its activity with December 31, 1997 and that the obligations within the Task 7 of the RAPSDRA project have been resumed by the ETH Integrated Systems Laboratory did not impact the regular development of the work.
4. Results and Conclusions
4.1 Review of the existing Reliability Simulators
New circuit design approaches based on the built-in reliability philosophy make use of tools such as reliability simulators. The goal of modern reliability simulators is to predict the circuit (or device) performance degradation as function of the time, and of different stresses (voltage, current, temperature, ...). This implies that reliability simulators have to include one or more physical models describing analytically the degradation of a given performance as a function of a stress parameter which is usually computed with a pre-processing circuit or device simulator (e.g. SPICE). Models which are currently implemented refer to the common wear-out failure mechanisms like hot carriers injection, electromigration, radiation effects, and time-dependent thin oxide breakdown
A very extensive literature search about the existing reliability simulators in microelectronics has been performed, and the related results have been included in the Report on the Chances of Reliability Simulation (M. Ciappa, Nov 21, 1997). The main conclusion was that at present status no reliability simulator for IGBT (and in general for power devices) is known in the literature. In converse, many papers have been published in the last 10 years on reliability simulators of integrated circuits (mostly digital), especially considering failure mechanisms like hot carrier injection and electromigration. Such simulators are available as commercial products. All the simulators have an interconnection model.
4.2 Statistical Data Analysis
The need of consistent data analysis tools has been expressed by many RAPSDRA partners. Basing on this request an guidelines have been developed which provides those tools for statistical design of experiments, statistical data analysis (failure rate metrology), failure rate prediction, availability computation, optimization of preventive maintenance, and spare part calculation. The failure rate metrology of lots which produces just some few failures has been especially investigated by the University of Parma. The related results have been published in a report authored by M. Cacciari, P. Cova, G. Franceschini, F. Fantini, and M. Ciappa.
4.3.1 Physical Failure Rate Modeling
The physical models of the dominant failure mechanisms have been investigated, in order to quantitatively describe the failure rate due to the dominant failure mechanisms. Of particular interest are those failures occurring within the lowest quantiles of the failure free distribution function. Special attention has been paid here to the breakdown (intrinsic and extrinsic) of thin gate oxides. A software package (basing on MatLab) has been developed which enables to compute the cumulative distribution and the failure rate (or survival rate) of a given sample as a function of the time, basing on a reference distribution (lognormal or Weibull). The program can be operated either by using custom-defined reference distributions, or by using a set of default parameters derived by past experiments.
4.3.2 Thermomechanical Related Failure Mechanisms
Analytical models which provide the number of thermal cycles to the failure for chip fatigue cracking, chip brittle cracking, bond-wire fatigue at the interface, bond-wire fatigue at the heel., and Solder Fatigue as a function of design and physical parameters have been listed, critically reviewed, and implemented in MatLab. Almost all models make use of the Coffin-Manson law, where physical parameters like temperature exclusion or maximum stress are required to be entered as an input. In order to provide realistic input parameters for these models some auxiliary programs have been developed which deliver good estimates of both the mechanical stresses in multilayered structures and of the steady-state surface temperature of a multilayered device. The default meterial parameters required by the end-of-life models are originated from literature data. Custom parameters (e.g. values measured in the framework of RAPSDRA) can be entered by the user for each calculation.
4.4 Lifetime Prediction at Converter Level
A consistent procedure for extarpolating the lifetime of IGBT devices operated in real locomotive environment has been proposed. It takes into account the dominant failure mechanisms (thermomechanics-related) and the application profile of the device. Results originated from Task 1 and Task 2 have been implemented in the model.
4.5 Failure Analysis Handbook
Support in failure analysis of IGBT modules has been required by various project partners. The development of a Failure Analysis Handbook was initially intended on one side to responding to this analysis demand, and on the other side to act as a compensation for the duties of the ETH in the framework of Task 2b (benchmarking), which could not be honored in 1996 and 1997 due to logistic reasons. The Handbook includes sample preparation techniques for silicon devices. The efficiency of those procedures has been tested during the last ten years especially at the ETH-Zurich. A special focus has been placed on the requirements imposed by the characterization and de-processing of IGBT modules.
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