ULTRA II: Ulsi most research activity II

• Forschungsstelle: EU FRP
• Projektnummer: 00.0213
• Projekttitel Englisch: ULTRA II: Ulsi most research activity II

Schlüsselwörter (Englisch)

MOS; MOSFET; submicron; device; cannel; ULSI; reliabiliy

Alternative Projektnummern (Englisch)

EU project number: EP 28300

Forschungsprogramme (Englisch)

EU-programme: 4. Frame Research Programme - 1.3 Telematic systems

Kurzbeschreibung (Englisch)

See abstract

Partner und Internationale Organisationen (Englisch)

Coordinator: STMicroelectronics SA (F)

Abstract (Englisch)

In the ULTRA II project, the LEG group at EPFL performed electrical characterization and reliability tests of Complementary Metal Oxide Semiconductor (CMOS) devices produced by various ULTRA II partners with different technology options and device architectures. In particular, we focused on devices made with an epi channel architecture by Infineon, on transistors with channel implants performed with heavy ions by IMEC and on MOS Field Effect Transistors (MOSFET) integrated by Philips with a channel implantation done through the gate (TGi technique). For all devices, EPFL focused on the gate oxide conduction and reliability, on the Si/SiO2 interface quality and on the transistor reliability. In addition, a new charge pumping technique was developed to perform single trap profiling.
For the performance of 100nm transistor, conventional doping profiles with a maximum at the surface or uniform doping distribution demand doping concentrations in the range of 1E18 cm-3. These high doping concentrations degrade the device characteristics. This is why the optimized channel doping profiles are considered as a key process module in order to minimize short channel effects, to adjust low threshold voltage values, to reduce junction capacitance and body effect and to avoid carrier mobility degradation due to high doping concentrations. From the epitaxial growth we can expect the steepest doping profiles, without implantation damage and annealing steps. Other important issues for such scaled devices are thin gate oxides, poly Si gates without depletion layers and shallow extensions for the source drain regions. Different measurement techniques are applied to characterize wafers without and with retrograde epi profiles produced by Infineon. Our results show the good quality of the gate dielectric. The measured fast interface trap density is low and is very similar for epi and reference wafers. The Stress Induced Leakage Current (SILC) effect is similar for the oxide grown on the epi and reference wafers.
Channel profiling is of great importance for the control of Short Channel Effect (SCE) in modern deep sub-micron CMOS transistors. It was shown recently that a good SCE behavior for nMOSFETs could be obtained by combining the HALO implant approach with indium channel doping. At the same time the impact of the heavy ions on the resistance to hot carrier (HC) effects should be investigated. We generated new experimental results on the HC degradation of the 100 nm nMOSFETs with and without heavy ion channel doping for devices integrating a 2 nm gate oxide. We did not observe any series resistance degradation. The HC reliability does not decreases after the heavy ion implantation. A 10 years DC lifetime can be reached for the MOSFETs with and without heavy ions.

It was shown recently that a good Short Channel Effect (SCE) behavior for nMOSFETs could be obtained by using Through the Gate Implantation (TGI) to form a boron super-steep retrograde channel doping profile. It was found that the charge to breakdown characteristics of gate oxides thinner than 6 nm are not degraded by the TGI process. At the same time the HC reliability of MOSFETs made with TGI was never investigated or reported. We therefore focused on the study of the HC degradation of devices made with the TGI technique and reported new experimental results for 100 nm nMOSFETs. We demonstrated that the TGI technique does not decrease the device resistance to HC stress. By using the CP technique we also showed that the Si/SiO2 interface trap density and its non-uniformity have been slightly increased due to TGI.
In scaled MOSFETs the number of interface traps becomes very small. The characteristics of such devices can be affected by charging and discharging of individual defects at the Si-SiO2 interface. The properties of a single trap have been studied extensively by Random Telegraph Signal (RTS) measurements. Recently, CP has also been used to investigate individual interface traps. To obtain the CP characteristic of a single trap small-size MOSFETs with low interface trap density have been used. We proposed and demonstrated a CP technique to extract the characteristic of a single trap located near the drain even in relatively large MOSFETs or in arrays of MOSFETs with common gates, common sources and separated drain contacts. In this case the total quantity of interface traps can be as high as several thousands.

Datenbankreferenzen (Englisch)

Swiss Database: Euro-DB of the
State Secretariat for Education and Research
Hallwylstrasse 4
CH-3003 Berne, Switzerland
Tel. [phone]
Swiss Project-Number: 00.0213