AUTOMACS: Advanced unified lateral DMOS transistor model for automotive circuit simulation

• Unité de recherche: PCRD EU
• Numéro de projet: 00.0009
• Titre du projet anglais: AUTOMACS: Advanced unified lateral DMOS transistor model for automotive circuit simulation

Mots-clé (Anglais)

High-voltage MOS transistors; compact modelling; circuit simulation; automotive applications

Autre Numéro de projet (Anglais)

EU project number: IST-1999-12257

Programme de recherche (Anglais)

EU-programme: 5. Frame Research Programme - 1.2.4 Essential technologies and infrastructures

Description succincte (Anglais)

See abstract

Partenaires et organisations internationales (Anglais)

Alcatel Microelectronics (B); Robert Bosch (D), EPFL (CH), IMEC (B), Silvaco Data Sytems (F)

Résumé des résultats (Abstract) (Anglais)

Lateral DMOS devices can handle voltages in the 20 - 100 V range and switch currents of several amperes. When integrated in sub-micron CMOS processes, they offer a unique combination of a signal processing capability together with high voltage interfaces and drivers. This CMOS-DMOS combination is especially suited for automotive and industrial applications. New automotive circuits integrate a transceiver to communicate over car-networks, a processor core providing the intelligence and DMOS power stages to drive hundreds of electrical motors in the car.
A standard MOS transistor model can not accurately model the DMOS behaviour. The state-of-the art solution today is to use a macro-model, which combines a ' standard ' transistor model with additional circuit elements. The goal of this project is twofold: (I) provide an improved macro-model and (II) develop and validate a compact analytical model. The devices considered are the true lateral DMOS and the extended drain MOS, further referenced as the xDMOS.
The project is organised in 7 work packages (WP). WP 1 deals with simulations that offer the device physics ground for the models and with test structures to extract the parameters. In WP 2, the improved macro-model is devised, including DC and AC parameters and the extraction procedure. WP 3 will result in the compact analytical DMOS model. WP 4 will start in the second project year and analyses the statistical variation of the model parameters. In WP 5, the models are extended to include parameter shifts due to voltage stressing over the lifetime of the device. In WP 6, the models are validated by the design and evaluations of high voltage building blocks; the models will be implemented in the circuit simulation tools used in the design of automotive circuits. WP 7 will organise and steer the dissemination activities.

Références bases de données (Anglais)

Swiss Database: Euro-DB of the
State Secretariat for Education and Research
Hallwylstrasse 4
CH-3003 Berne, Switzerland
Tel. [phone]
Swiss Project-Number: 00.0009