Visual-Servoing Testbed with AI-Hardware in the Loop

• Unité de recherche: SEFRI
• Numéro de projet: P2024-HSLU VSTB

Mots-clé (Anglais)

Hochschule Luzern Visual-Servoing Testbed with AI-Hardware in the Loop Jürgen Wassner SBFI SERI SEFRI SSO ARF

Description succincte (Anglais)

In this project a Visual-Servoing Testbed (VSTB) for development and test of a Smart Space Camera (SSC) shall be designed and stepwise taken into operation. The VSTB will use a first functional hardware model of the SSC, which shall be integrated in parallel with the VSTB within this project. The SSC then is to be developed according to product requirements in a follow-up project using the VSTB.
The conceived SSC shall enable autonomous navigation by using a single high-resolution image sensor with a fixed-focal length lens, to provide pose estimation of target objects to the GNC unit of the satellite. The SSC also performs digital zooming to maintain a reasonable pixel resolution for objects at different distances, and employes AI models for pose estimation. The basic concept of such an SSC and its realization in a single space-qualifiable FPGA has been proven by a previous feasibility study financed by ESA and performed by HSLU [1]. To advance the conceptual design of the SSC from TRL 3 to TRL 4, a functional hardware model of the SSC shall be implemented within this project. This functional model together with the visual-servoing testbed will enable hardware-in-the-loop simulation. With this approach, the project addresses the chicken-and-egg problem of how to assess the testbed without a device under test being available yet.
The VSTB to be developed serves multiple purposes during various stages of the design process. Since it considers overall system dynamics in each of these stages, it will be a valuable tool for the future requirements-based development of the product SSC as well as for any further research and development activities on vision-based navigation systems.

Objectifs du projet (Anglais)

The goal of this project is to advance the conceptual design of the SSC from TRL 3 to TRL 4 by enabling hardware-in-the-loop simulation. To achieve this, this project shall:
a) implement a first functional hardware model of the SSC,
b) realize a multi-purpose Visual-Servoing Testbed (VSTB), and
c) iteratively integrate and take both into operation.
Finally, independent lab-testing in a target-like environment using non-synthetic imagery will provide valuable information both about the robustness of the SSC and the effectiveness of the developed testbed.