Abstract
(Englisch)
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Deployment of intelligence at the edge presents many challenges because devices need to be low-cost and, as such, they
are often constrained in computing capacity, memory, and energy resources.
These constraints are not compatible with the need for much more advanced AI algorithms calling for Mbytes of storage
and tens of GOPS per inference and call for leaner edge AI algorithms. The current state of the art for (the few) edge-
AI chips relies on low-cost process technologies at 90 or 40nm and in some cases up to 16nm, with power efficiency
between 1-5 TOPS/w and power densities up to 1 TOPS/mm2.
Recently several industrial projects and a few products have started to surface pursing neuromorphic and in memory
computing, but none of these efforts have reached a level of maturity compatible with a mass volume production and
cost, and, moreover the technology base they rely on is either not scalable to more advanced nodes (flash) or, targeting
AI computing algorithms whose practical applications are yet to be fully proven (e.g., spiking). The NeuroSoC approach
instead is to rely on a solid, mature, and qualified reliable Phase Change Memory technology to create an industrially
proven path to go past the state of the art, as such, the NeuroSoC chip pre-product demonstration of the technology will
be the first of his kind worldwide.
NeuroSoC’s aim is to develop an advanced Multi-Processor System on Chip prototype in FD-SOI 28nm CMOS
technology that tightly integrates an AIMC IMNPU unit, a local digital processing subsystem, and functional safe
multiprocessor host subsystems based on an enhanced version of existing RISC-V microprocessor implementation, while
covering IMNPU security aspects holistically to tackle the requirements of a wide set of edge-AI applications.
The project will leverage STMicroelectronics’s unique high-density embedded PCM cell process technology being the
denser and only such technology qualified and mature for embedded use in the industry world
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