Abstract
(Englisch)
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REMINDER aims to develop an embedded DRAM solution optimized for ultra-low-power consumption and\nvariability immunity, specifically focused on Internet of Things cut-edge devices. The objectives of REMINDER are :\ni) Investigation (concept, design, characterization, simulation, modelling), selection and optimization of a\nFloating-Body memory bit cell in terms of low power and low voltage, high reliability, robustness\n(variability), speed, reduced footprint and cost.\nii) Design and fabrication in FDSOI 28nm (FD28) and FDSOI 14nm (FD14) technology nodes of a\nmemory matrix based on the optimized bit-cells developed. Matrix memory subcircuits,\nblocks and architectures will be carefully analysed from the power-consumption point of view.\nIn addition variability tolerant design techniques underpinned by variability analysis and statistical\nsimulation technology will be considered.\niii) Demonstration of a system on chip application using the developed memory solution and\nbenchmarking with alternative embedded memory blocks.\nThe eventual replacement of Si by strained Si/SiGe and III-V materials in future CMOS circuits would also\nrequire the redesign of different applications, including memory cells, and therefore we also propose the evaluation\nof the optimized bit cells developed in FD28 and FD14 technology nodes using these alternative\nmaterials. \nThe fulfilment of the objectives above will also imply the development of:\ni) New techniques for the electrical characterization of ultimate CMOS nanometric devices. This will\nallow us to improve the CMOS technology by boosting device performance.\nii) New behavioural models, incorporating variability effects, to reach a deep understanding of\nnanoelectronics devices\niii) Advanced simulation tools for nanoelectronic devices for state of the art, and emerging devices.\niv) Extreme low power solutions\nThe consortium supporting this proposal is ideally balanced with 2 industrial partners, 2 SMEs, 2 research centers and 3 universities.
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