Design Tools for Networks-on-Chip: automatically building on-chip Internets for next-generation chips.

• Research unit: INNOSUISSE
• Project number: 10046.2;8 PFNM-NM

Short description (English)

Design Tools for Networks-on-Chip: automatically building on-chip Internets for next-generation chips.

Short description (French)

Design Tools for Networks-on-Chip: automatically building on-chip Internets for next-generation chips.

Abstract (English)

Networks-on-Chip (NoCs) are the technology of the future to interconnect and integrate the building blocks within next-generation multimedia chips. The deployment of this breakthrough technology needs suitable design tools in order to shorten design times and improve the performance of the resulting chips. This project aims at making NoCs commercially viable by providing a cutting-edge set of implementation tools, leading to a potential revenue of more than US1 million per design win.

Abstract (French)

Networks-on-Chip (NoCs) are the technology of the future to interconnect and integrate the building blocks within next-generation multimedia chips. The deployment of this breakthrough technology needs suitable design tools in order to shorten design times and improve the performance of the resulting chips. This project aims at making NoCs commercially viable by providing a cutting-edge set of implementation tools, leading to a potential revenue of more than US1 million per design win.