DVB-T2 advanced software platform

• Forschungsstelle: INNOSUISSE
• Projektnummer: 9900.1;3 PFNM-NM
• Projekttitel Englisch: DVB-T2 advanced software platform

Kurzbeschreibung (Englisch)

DVB-T2 advanced software platform

Kurzbeschreibung (Französisch)

DVB-T2 advanced software platform

Abstract (Englisch)

From the algorithmic point of view, the LDPC decoding complexity can be up to 2000 times the Viterbi decoding while the time allowed to acquire a channel in DVB-T2 is four time DVB-T. This represents a formidable challenge that we propose to address in this project together with EPFL Mobile Communications laboratories, which have unique experience in LDPC techniques and signal acquisition. The objective of the DASP (DVB-T2 advanced simulation platform) project is to address the two most critical components of DVB-T2 and to provide guidelines for the design of a DVB-T2 receiver chip, with the following aims: ¿ reduce by at least a factor of ten the complexity of the forward error correction decoder ¿ reduce acquisition times to make them at least comparable with that of DVB-T ¿ implement a complete DVB-T2 simulation platform, including transmitter and receiver, to support a receiver system on chip implementation The deliverables of the DASP project are 1) a complete DVB-T2 simulator, 2) a FPGA connected to the Abilis RF tuner to validate the synchronization and 3) a core IP RTL targeted for implementation into a CMOS 65nm product. These deliverables will enable Abilis to build the most competitive DVB-T2 solution in the market place.

Abstract (Französisch)

From the algorithmic point of view, the LDPC decoding complexity can be up to 2000 times the Viterbi decoding while the time allowed to acquire a channel in DVB-T2 is four time DVB-T. This represents a formidable challenge that we propose to address in this project together with EPFL Mobile Communications laboratories, which have unique experience in LDPC techniques and signal acquisition. The objective of the DASP (DVB-T2 advanced simulation platform) project is to address the two most critical components of DVB-T2 and to provide guidelines for the design of a DVB-T2 receiver chip, with the following aims: ¿ reduce by at least a factor of ten the complexity of the forward error correction decoder ¿ reduce acquisition times to make them at least comparable with that of DVB-T ¿ implement a complete DVB-T2 simulation platform, including transmitter and receiver, to support a receiver system on chip implementation The deliverables of the DASP project are 1) a complete DVB-T2 simulator, 2) a FPGA connected to the Abilis RF tuner to validate the synchronization and 3) a core IP RTL targeted for implementation into a CMOS 65nm product. These deliverables will enable Abilis to build the most competitive DVB-T2 solution in the market place.