ESCRYPT-II:Quantum Cryptography based point-to-point Secure Data Communication System (Phase II)

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Projektnummer

9821.1;3 PFNM-NM

Projekttitel

ESCRYPT-II:Quantum Cryptography based point-to-point Secure Data Communication System (Phase II)

Projekttitel Englisch

ESCRYPT-II:Quantum Cryptography based point-to-point Secure Data Communication System (Phase II)

Texte zu diesem Projekt

	Deutsch	Französisch	Italienisch	Englisch
Kurzbeschreibung	-	-	-
Abstract	-	-	-

Erfasste Texte

Kategorie	Text
Kurzbeschreibung (Englisch)	ESCRYPT-II:Quantum Cryptography based point-to-point Secure Data Communication System (Phase II)
Abstract (Englisch)	In 2010 to 2012, 40 and 100 Gbps Ethernet will be used. id Quantique needs to adapt its 10 Gbps Quantum-Key- Distribution based cryptographic system to these rates in order to stay a strong competitor on the market. Standardization in progress and customer demands require high flexibility during the product introduction, which FPGA solutions can provide. However, 40-to-100 Gbps cipher engines in FPGAs are a hard challenge. Since authentication at these throughputs is comparably computation-intensive as encryption, a HW solution will be a strong commercial advantage, if not an absolute must. However, it makes the FPGA design even more challenging.

Kategorie

Text

Kurzbeschreibung
(Englisch)

ESCRYPT-II:Quantum Cryptography based point-to-point Secure Data Communication System (Phase II)

Abstract
(Englisch)

In 2010 to 2012, 40 and 100 Gbps Ethernet will be used. id Quantique needs to adapt its 10 Gbps Quantum-Key- Distribution based cryptographic system to these rates in order to stay a strong competitor on the market. Standardization in progress and customer demands require high flexibility during the product introduction, which FPGA solutions can provide. However, 40-to-100 Gbps cipher engines in FPGAs are a hard challenge. Since authentication at these throughputs is comparably computation-intensive as encryption, a HW solution will be a strong commercial advantage, if not an absolute must. However, it makes the FPGA design even more challenging.