FAST Pricer: FPGA-based Accelerating Solution for Parallel Synthetic CDO Pricer

• Research unit: INNOSUISSE
• Project number: 9706.1;4 PFES-ES

Short description (English)

FAST Pricer: FPGA-based Accelerating Solution for Parallel Synthetic CDO Pricer

Short description (French)

FAST Pricer: FPGA-based Accelerating Solution for Parallel Synthetic CDO Pricer

Abstract (English)

Financial business has a growing need for computational performances in order to price new complex instruments (MBS, CDO, etc) requiring more and more processing time. To sustain this demand upgrading servers, or adding computers to farms would not be enough. Other specific solutions must be found to address the appetite for CPU intensive algorithms. The aim of the project is to develop a prototype of a reconfigurable arithmetic accelerating board based on FPGA able to perform fast pricing of the synthetic CDO instrument. Besides this main goal, the project aims at exploring the usage of FPGA acceleration boards in finance applications on a broader scale.

Abstract (French)

Financial business has a growing need for computational performances in order to price new complex instruments (MBS, CDO, etc) requiring more and more processing time. To sustain this demand upgrading servers, or adding computers to farms would not be enough. Other specific solutions must be found to address the appetite for CPU intensive algorithms. The aim of the project is to develop a prototype of a reconfigurable arithmetic accelerating board based on FPGA able to perform fast pricing of the synthetic CDO instrument. Besides this main goal, the project aims at exploring the usage of FPGA acceleration boards in finance applications on a broader scale.