High Speed Communication Receiver in CMOS for 40 Gb/s Serial Optical Link (HIGHSCORE)

• Research unit: INNOSUISSE
• Project number: 7995.1;5 NMPP-NM

Short description (German)

High Speed Communication Receiver in CMOS for 40 Gb/s Serial Optical Link (HIGHSCORE)

Short description (English)

High Speed Communication Receiver in CMOS for 40 Gb/s Serial Optical Link (HIGHSCORE)

Abstract (German)

The focus of the project is the development of a demonstrator of a receiver with an optical 40 Gb/s input (InP-pin pho-todiode and CMOS preamplifier) and 4x10 Gb/s demultiplexed electrical outputs. The electronic system will operate at sub-rate (i.e. internal clock frequencies will be 20 GHz or less) and must not comprise external components (except a quartz reference). Because a parallel deployment of the resulting system on a single chip for parallel data transmission is projected, all components of the clock-data-recovery loop must be fully digital and will therefore be implemented in CMOS technology. The final goal will be to start a product integration of an optical/electrical conversion module hav-ing a 40Gb/s optical input and 4x10Gb/s electrical outputs.

Abstract (English)

The focus of the project is the development of a demonstrator of a receiver with an optical 40 Gb/s input (InP-pin pho-todiode and CMOS preamplifier) and 4x10 Gb/s demultiplexed electrical outputs. The electronic system will operate at sub-rate (i.e. internal clock frequencies will be 20 GHz or less) and must not comprise external components (except a quartz reference). Because a parallel deployment of the resulting system on a single chip for parallel data transmission is projected, all components of the clock-data-recovery loop must be fully digital and will therefore be implemented in CMOS technology. The final goal will be to start a product integration of an optical/electrical conversion module hav-ing a 40Gb/s optical input and 4x10Gb/s electrical outputs.