Hardware and software implementation of new scalable and parallel symmetric cipher

Fonte Standard Gras
Identifiant

Unité de recherche

INNOSUISSE

Numéro de projet

7645.1;10 NMPP-NM

Titre du projet

Hardware and software implementation of new scalable and parallel symmetric cipher

Titre du projet anglais

Hardware and software implementation of new scalable and parallel symmetric cipher

Textes relatifs à ce projet

	Allemand	Français	Italien	Anglais
Description succincte	-	-	-
Résumé des résultats (Abstract)	-	-	-

Textes saisis

Catégorie	Texte
Description succincte (Anglais)	Hardware and software implementation of new scalable and parallel symmetric cipher
Résumé des résultats (Abstract) (Anglais)	This project aims at implementing a cryptographic algorithm from Cryptonics Systems to achieve encryption in the 1-10 Gbps throughput range. The algorithm, whose design principles arise from physics instead of mathematics, is very flexible and thus perfectly suited to address material constraints of diverse hardware implementation such as FPGA, integrated circuits or GPUs. It is also parallel and scalable, thus parallel hardware is favoured to achieve best results.

Catégorie

Texte

Description succincte
(Anglais)

Hardware and software implementation of new scalable and parallel symmetric cipher

Résumé des résultats (Abstract)
(Anglais)

This project aims at implementing a cryptographic algorithm from Cryptonics Systems to achieve encryption in the 1-10 Gbps throughput range. The algorithm, whose design principles arise from physics instead of mathematics, is very flexible and thus perfectly suited to address material constraints of diverse hardware implementation such as FPGA, integrated circuits or GPUs. It is also parallel and scalable, thus parallel hardware is favoured to achieve best results.