ET4US: Epitaxial technologies for ultimate scaling

• Unité de recherche: PCRD EU
• Numéro de projet: 03.0419-2
• Titre du projet anglais: ET4US: Epitaxial technologies for ultimate scaling

Mots-clé (Anglais)

High mobility; transistors; high-k gate dielectrics

Autre Numéro de projet (Anglais)

EU project number: 002048

Programme de recherche (Anglais)

EU-programme: 6. Frame Research Programme - 1.2 Communications technologies

Description succincte (Anglais)

See abstract

Autres indications (Anglais)

Full name of research-institution/enterprise:
EPF Lausanne
Faculté de sciences de base IPMC
Institut de physique de la matière complexe LNNME

Résumé des résultats (Abstract) (Anglais)

Silicon CMOS is rapidly running out of steam and the entire semiconductor industry is puzzled about what comes next as the roadmap advances towards the terahertz region. It is clear that virtually every material (gate, gate oxide and channel) used in the current transistor must be replaced within the next 3 - 4 years, without interruption in the industry's pace. Two high mobility material classes are emerging as potential silicon replacement: germanium (Ge) and compound semiconductors (CS). The goal of this project is to find out which one presents the best future technology platform. This formidable question requires a major rethinking of all materials and processes. It will be addressed here from all relevant aspects: advanced large area wafers, novel gate stacks and transistor processing. With a strict focus on a simple and well defined process-flow as well as an innovative, fast materials characterization track, the main strengths and show-stoppers for each material system will be identified. The first objective is to demonstrate that high mobility large area compliant substrates of Ge-on-insulator (GOI) and CS-on-insulator (CSOI) can be obtained. GOI and CSOI will be grown by developing a 'strained oxide template on Si' technology based on molecular beam epitaxy (MBE). The second objective is to demonstrate high quality gate stacks on Ge and CS. The challenge is to find suitable high-k compounds that can be used as gate dielectrics while maintaining high channel mobilities. The development of amorphous or epitaxial (for double gate) metal gates are also an essential project component. The third objective is to integrate the new channel and gate materials with a 200 mm semiconductor wafer processing line to demonstrate high mobility transistors for a few well chosen material systems.

Références bases de données (Anglais)

Swiss Database: Euro-DB of the
State Secretariat for Education and Research
Hallwylstrasse 4
CH-3003 Berne, Switzerland
Tel. [phone]
Swiss Project-Number: 03.0419-2