WALORI: Wafer level optics solution for compact CMOS imager

• Forschungsstelle: EU FRP
• Projektnummer: 01.0569-2
• Projekttitel Englisch: WALORI: Wafer level optics solution for compact CMOS imager

Schlüsselwörter (Italienisch)

Information Processing; Information Systems; Innovation; Technology Transfer

Alternative Projektnummern (Englisch)

EU project number: IST-2001-35366

Forschungsprogramme (Englisch)

EU-programme: 5. Frame Research Programme - 1.2.4 Essential technologies and infrastructures

Kurzbeschreibung (Englisch)

See abstract

Abstract (Englisch)

This project aims at demonstrating the feasibility of an ultra-compact low cost camera module including CMOS image sensor, image processing and built-in lens:
- By developing ultra-thin optical systems to be delivered in a wafer form ready for subsequent bonding to the image sensor wafer;
- By developing a specific wafer thinning technique and by designing a specific thinned sensor compatible with backside illumination to decrease module thickness and to improve camera sensitivity;
- By defining a wafer level camera assembly flow (wafer thinning, collective bonding of the optical wafer to the image sensor wafer and collective testing).
Two different types of ultra-thin optics wafers will be collectively bonded to thinned silicon wafers for full evaluation, the ultimate goal being to prove the cost effectiveness and performance of the collective camera module manufacturing technique and its applicability to mobile applications.

Objectives:
The key objectives of the present project are:
- To demonstrate an advanced CMOS camera module concept (including image sensor, processing, built-in lens bonded to the chip) able to bring a real breakthrough on high volume market for telecom and multimedia applications in terms of: integration and compactness, sensor detectivity, image quality, manufacturability;
- To master the main bricks of this concept and to find the right trade off Cost/Performances/Product;
- To develop new optical concepts allowing thin optical system to be directly bonded on image sensor silicon wafer and able to meet at least the same optical performance as current macro imaging systems;
- To design and characterize it;
- To develop highly collective assembly techniques enabling a full wafer scale processing for the complete camera module;
- To enhance the overall camera sensitivity by developing a wafer level thinning process and by designing highly responsive thinned CMOS image sensor to be backside illuminated.

Work description:
Once general product specification elaborated together with all participants (WP1), the project will be divided in two major phases:
Phase 1: Parallel Designs and prototyping of optical imaging system and thinned CMOS image sensor, development of bonding and thinning process;
Phase 2: Assembly of components prototyped in phase 1 and final demonstrator characterisation.
Phase 1 is partitioned in three work packages corresponding to main domains: optics (WP2), silicon sensor (WP3) and assembly process (WP4):
- Design and prototyping of imaging thin optical wafer. Various concepts compatible with thin imaging will be evaluated through design operations. First wafer prototype characterisation will enable selection of best solutions, their optimisation and final prototyping;
- Design and prototyping of thinned CMOS sensor. Special attention will be paid on crucial aspects like thin substrate effect on potential control during mixed circuit operation or backside treatment for circuit and transistors light masking. Simulation will be extensively used to overcome these key points. Wafer lot will be then processed. Wafer level test, final module assembly and characterisation means will be developed in this work package too;
- Development of bonding + thinning process. Two different bonding techniques will be developed, one for silicon and optical wafers assembly, the other for silicon thinning process. Alignment methods and backside treatments will be considered too.
Phase 2 is composed of one work package (WP5) and consists in:
- Wafer scale assembly. Final optical wafers will be bonded with thinned silicon wafer;
- Image module simulation. Stacked wafer will be sawed into individual modules, which will be finally packaged;
- Electro-optical characterisation of final prototype will be then performed.

Milestones:
M1.1: Prealable product top specification;
M2.1: Opto-wafer prototyping;
M2.2: Comparison of opto-wafer concepts;
M3.1: Thinned CMOS Sensor Design phase end;
M3.2: First Silicon Wafer Lot availability & testing;
M3.3: 2nd Lot availability & testing;
M4.1: Thinned CMOS wafers on handle: major step demonstration of thinning process;
M4.2: Dummy silicon wafer bonded on optical wafer;
M4.3: Thinned CMOS wafer bonded and aligned on optical wafer;
M5.1: Final demonstrator availability;
M5.2: Final evaluation report

Datenbankreferenzen (Englisch)

Swiss Database: Euro-DB of the
State Secretariat for Education and Research
Hallwylstrasse 4
CH-3003 Berne, Switzerland
Tel. [phone]
Swiss Project-Number: 01.0569-2