Partner und Internationale Organisationen
(Englisch)
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RIBER S.A. (F), Oxford Applied Research Ltd. (UK), Interuniversitair Micro-Elektronica Centrum (B), National Center for Scientific Research "Demokritos", Institute of Materials Science (EL), Max Planck-Institut Halle (D), Istituto Nazionale per la Fisica della Materia, Laboratorio MDM (I), Clausthal University of Technology (D), Philips Innovative Technology Solutions (B)
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Abstract
(Englisch)
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We aim at integrating advanced complex metal oxide (CMOX) materials, exhibiting superior properties, with Silicon CMOS technology to enhance the high frequency performance and increase the density and functionality of integrated circuits. We primarily plan to use the high dielectric constant property of CMOX[s] to replace the SiO2 at the gate of transistors aiming at an equivalent oxide thickness in the range between 0.5 and 0.8 nm in order to downscale the transistors in the deep sub-micron range (<100 nm). To optimally exploit the materials properties, direct deposition of CMOXs on Silicon is required, so that Molecular Beam Epitaxy is employed to finely control the growth with monolayer precision using state-of-the-art, real time characterization tools. This allows control of stoichiometry and interfaces to prevent oxidation of the underlying Si and minimize interface defect densities. The final evaluation of the material will be performed on 0.18 µm (or next generation) CMOS transistors with high-k gates fabricated by the replacement gate method to ensure that performance & reliability is comparable to that of conventional SiO[2] devices.
Objectives:
The general objective is to overcome technology barriers to enhance high frequency performance and increase the density, storage capacity and functionality of ICs. Our primary sub-objective will be to demonstrate that complex metal oxides (CMOX) exhibiting very high dielectric constant k are suitable for the replacement of SiO[2] gate in deep-submicron technology (<100 nm) and that they can be integrated with part of silicon CMOS technology. This will be achieved by developing appropriate methodology, based on molecular beam epitaxy (MBE), for the deposition of high-k (k>20) CMOX materials. Our secondary sub-objective is to introduce novel materials combinations to combine increased functionality (e.g. non-volatility) and density in storage devices with enhanced performance in PMOSFETs.
The success of the project will be evaluated according to the following technical objectives:
(a) Obtain high and/or medium k CMOX layers with high structural and electrical quality on silicon. Target value for the equivalent oxide thickness (EOT) is 0.5-0.8 nm.
(b) Demonstrate a reliable oxide MBE tool capable of oxide growth on large area (8 inch) wafers.
(c) Demonstrate successful integration of MBE-grown high-k CMOX layer with 0.18 µm (or nextgeneration) CMOS technology. This will be verified by fabricating functional MOSFETs with kigh-k gates and EOT<1 nm using the replacement gate process.
Work description:
The work will be organized in five project-specific workpackages (WP):
WP1- Modeling,
WP2- Growth and Equipment Development,
WP3- Characterization,
WP4-Transistor Fabrication,
WP5- Device Testing.
Phase 1 (first 24 months): Materials research and growth process development
During Phase 1, priority will be given to the evaluation of the (very) high-k candidate materials for the replacement of SiO[2] gate.
In WP1, growth simulation using ab-initio molecular dynamics will help focusing the growth effort on the most suitable complex metal-oxides (CMOX) which are thermodynamically compatible with silicon and form stable interfaces.
In WP2 we will first grow and determine the stability of various high-k candidates on small size Si wafers.
Second we will employ appropriate sources and real-time monitoring methods for the heteroepitaxial growth, especially on preprocessed CMOS substrates where excellent control of deposition conditions is required to prevent damage and contamination of the underlying active channel.
Both WP1 and WP2 will target the first technical objective to obtain high structural and electrical quality CMOX thin-films and interfaces verified by using high-resolution transmission electron microscopy and X-ray diffraction in WP3.
In WP5, using generic MIS capacitors we plan to test the dielectric response of the CMOX films. During this time, the new large wafer area oxide MBE tool will be designed, manufactured, delivered and installed aiming at technical objective 2.
Completion of these activities will mark the end of Phase 1, at which time the best material candidate will be selected to proceed with transistor fabrication in Phase 2.
Phase 2 (last 12 months): Integration of high-k materials with the prevailing CMOS technology
During Phase 2, there will be two parallel activities the largest of which will be associated with the integration of high-k materials (WP4) while the other will target the development of novel materials combination such as ferroelectric CMOX/Si and CMOX/SiGe (WP2).
In WP4, the replacement gate method will be used to fabricate short-channel (0.18 µm or shorter) CMOS with high-k gates on 8 inch preprocessed wafers. Particular effort will be devoted to control cross-contamination so that the novel MBE growth step of CMOX gate materials can be introduced without disrupting the operation of an 8-inch wafer processing line.
In WP5, the CMOS transistors will be tested to demonstrate performance (especially channel mobility) and reliability comparable to that of conventional SiO[2] devices targeting technical objective 3. This will mark the end of Phase 2 and will complete the evaluation of the material at the most advanced level permitted by the present-day technology. It is expected that by the end of the project we will be able to determine to what extent the high-k candidate can withstand the demanding processing conditions and can give reliable transistor operation.
Milestones:
(1) Short list of MOs with adequate structural & electrical quality
(2) Operational and reliable oxide MBE prototype for growth on large area (8 inch) wafers.
(3) Obtain EOT < 0.8 nm from CV measurements on MIS capacitors.
(4) Fabrication of short-channel (0.18 µm or shorter) CMOS with high-k gates.
(5) Obtain functional high-k CMOS, with channel mobility values comparable to those of SiO[2] devices.
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