Abstract
(Englisch)
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This project will develop a new family of devices and systems which may lead to radically new alternatives to integrated circuit manufacturing, materials and design in contrast to currently forecast ultimate silicon technologies. The proposed novel circuits rely upon the molecular and atomic properties of the fullerenes and endohedral fullerenes for their manufacture and operation. The development of the technology requires new device concepts and novel new architectures for logic and memory operation. Device fabrication will be performed on the scale of tens of nanometer range and memory cells with dimension of a nanometer, the ultimate limit set by the size of the fullerene cage, will be assessed using a novel new nanofabrication technique. To achieve this goal, a gathering of expertise from the fields of physics, chemistry, materials science, nanotechnology and microelectronics will be leveraged to solve the trans-disciplinary nature of the work.
Objectives:
The primary objective of the NICE project is to develop a buckminsterfullerene based nano-integrated circuit technology capable of providing data processing and storage capabilities. To achieve this goal, development work for endohedral materials production, design and modelling, characterisation of nanocircuits, and optimisation and extension of direct patterning nanofabrication techniques will be undertaken. A demonstrated capability for the application of nanofabrication techniques to produce both logic and memory functions on the nanoscale serves as the basis for developing future computing circuits on length scales approaching atomic dimensions. The circuit demonstrators proposed within the NICE project reflects two-orders of magnitude greater integration density than current commercial R&D technologies while providing a direct route to atomic level integration densities of 100 terabits/cm2. The project rests upon joining and further development of two new technologies: endohedral buckminsterfullerene production and the nanostencil technique.
Work description:
To achieve the goal of developing a practical approach to nanoscale computing, developments in four categories will be pursued within the NICE project: endohedral buckminsterfulerene production, simulation and design, nanofabrication, and electrical and circuit characterisation. Endohedral fullerenes can be produced in which one, two or three metal atoms are captured within the fullerene cages but up until very recently slow progress with the isolation and purification of these materials has delayed their study in macroscopic amounts. A breakthrough has occurred with the development of a new production method. The method is the only means available which allows the production and isolation of macroscopic amounts of endohedrally doped C60 molecules. An innovative aspect of the NICE project is the additive approach taken to nanofabrication. Typical microelectronics patterning requires 'deposition-pattern-etching' with several associated sub-steps. The combination of the shadow masking technique with scanning probe methods allows structures to be deposited locally through pin-hole like apertures within the proximity of the cantilever tip. Predefined excursions of the sample lead to the direct fabrication of arbitrary structures on the tens of nanometer length scale. With this approach, the material composition of the as-deposited fullerene line can be varied allowing for the formation of junctions within a single layer. Arbitrary two-dimensional structures can be fabricated with arbitrary material compositions (four sources may be used for deposition into a single layer). This allows for the formation of a truly planar integrated circuit technology, where various deposited materials are found in a single layer. The objective of the modelling and simulation work is to develop and apply models of the endohedral fullerene circuits to aid in design and integration. The tasks within the workpackage range from electronic structure calculation, through modelling of fullerene wires and junctions, to circuit lay-outs and analysis. Given optimised device structures, their integration into logic gates will be performed. The goal of this part of the project is specification of circuit topologies and critical dimensions for the nanofabrication workpackage. Two types of devices will be considered for integration: a nanoscale analog of MESFETs and 'planar' Schottky diodes. Low and room temperature electrical characterisation and electrical stress investigations will be performed.
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