Network on Chip (NoC) based FPGA Design Environment for Xilinx UltraScale Devices MIP: IOxOS Technologies SA

Research unit

INNOSUISSE

Project number

17187.1 PFES-ES

Project title

Network on Chip (NoC) based FPGA Design Environment for Xilinx UltraScale Devices MIP: IOxOS Technologies SA

Project status	Finished

Start date	01.12.2014
End date	01.01.2017

Granted total costs	234'100.00 CHF
Section	21 Förderbereich Enabling Sciences
Project category	Project
Research type	Applied research and development
NABS classification	Industrial production and technology

Research disciplines	100 % T180 Telecommunication engineering

Last modification of the project 29.07.2021